diff --git a/src/gallium/drivers/iris/iris_blorp.c b/src/gallium/drivers/iris/iris_blorp.c index e887e63e9e1..711477aa8ed 100644 --- a/src/gallium/drivers/iris/iris_blorp.c +++ b/src/gallium/drivers/iris/iris_blorp.c @@ -200,7 +200,7 @@ blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *blorp_batch, UNUSED uint32_t *sizes, unsigned num_vbs) { -#if GEN_GEN < 11 +#if GFX_VER < 11 struct iris_context *ice = blorp_batch->blorp->driver_ctx; struct iris_batch *batch = blorp_batch->driver_batch; bool need_invalidate = false; @@ -259,7 +259,7 @@ iris_blorp_exec(struct blorp_batch *blorp_batch, struct iris_context *ice = blorp_batch->blorp->driver_ctx; struct iris_batch *batch = blorp_batch->driver_batch; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 /* The PIPE_CONTROL command description says: * * "Whenever a Binding Table Index (BTI) used by a Render Target Message @@ -288,7 +288,7 @@ iris_blorp_exec(struct blorp_batch *blorp_batch, iris_require_command_space(batch, 1400); -#if GEN_GEN == 8 +#if GFX_VER == 8 genX(update_pma_fix)(ice, batch, false); #endif @@ -298,7 +298,7 @@ iris_blorp_exec(struct blorp_batch *blorp_batch, params->y1 - params->y0, scale); } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 genX(invalidate_aux_map_state)(batch); #endif diff --git a/src/gallium/drivers/iris/iris_query.c b/src/gallium/drivers/iris/iris_query.c index d039f86a6d1..9e161ae134d 100644 --- a/src/gallium/drivers/iris/iris_query.c +++ b/src/gallium/drivers/iris/iris_query.c @@ -158,7 +158,7 @@ iris_pipelined_write(struct iris_batch *batch, { const struct gen_device_info *devinfo = &batch->screen->devinfo; const unsigned optional_cs_stall = - GEN_GEN == 9 && devinfo->gt == 4 ? PIPE_CONTROL_CS_STALL : 0; + GFX_VER == 9 && devinfo->gt == 4 ? PIPE_CONTROL_CS_STALL : 0; struct iris_bo *bo = iris_resource_bo(q->query_state_ref.res); iris_emit_pipe_control_write(batch, "query: pipelined snapshot write", @@ -184,7 +184,7 @@ write_value(struct iris_context *ice, struct iris_query *q, unsigned offset) case PIPE_QUERY_OCCLUSION_COUNTER: case PIPE_QUERY_OCCLUSION_PREDICATE: case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: - if (GEN_GEN >= 10) { + if (GFX_VER >= 10) { /* "Driver must program PIPE_CONTROL with only Depth Stall Enable * bit set prior to programming a PIPE_CONTROL with Write PS Depth * Count sync operation." @@ -317,7 +317,7 @@ calculate_result_on_cpu(const struct gen_device_info *devinfo, q->result = q->map->end - q->map->start; /* WaDividePSInvocationCountBy4:HSW,BDW */ - if (GEN_GEN == 8 && q->index == PIPE_STAT_QUERY_PS_INVOCATIONS) + if (GFX_VER == 8 && q->index == PIPE_STAT_QUERY_PS_INVOCATIONS) q->result /= 4; break; case PIPE_QUERY_OCCLUSION_COUNTER: @@ -424,7 +424,7 @@ calculate_result_on_gpu(const struct gen_device_info *devinfo, } /* WaDividePSInvocationCountBy4:HSW,BDW */ - if (GEN_GEN == 8 && + if (GFX_VER == 8 && q->type == PIPE_QUERY_PIPELINE_STATISTICS_SINGLE && q->index == PIPE_STAT_QUERY_PS_INVOCATIONS) result = mi_ushr32_imm(b, result, 2); diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 2aa27f20991..335f706abab 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -419,7 +419,7 @@ flush_before_state_base_change(struct iris_batch *batch) * * STATE_BASE_ADDRESS * * 3DSTATE_BINDING_TABLE_POOL_ALLOC */ - ((GEN_GEN == 12 && devinfo->revision == 0 /* A0 */ ? + ((GFX_VER == 12 && devinfo->revision == 0 /* A0 */ ? PIPE_CONTROL_FLUSH_HDC : 0))); } @@ -626,7 +626,7 @@ iris_copy_mem_mem(struct iris_batch *batch, static void emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline) { -#if GEN_GEN >= 8 && GEN_GEN < 10 +#if GFX_VER >= 8 && GFX_VER < 10 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT: * * Software must clear the COLOR_CALC_STATE Valid field in @@ -666,9 +666,9 @@ emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline) PIPE_CONTROL_INSTRUCTION_INVALIDATE); iris_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) { -#if GEN_GEN >= 9 - sel.MaskBits = GEN_GEN >= 12 ? 0x13 : 3; - sel.MediaSamplerDOPClockGateEnable = GEN_GEN >= 12; +#if GFX_VER >= 9 + sel.MaskBits = GFX_VER >= 12 ? 0x13 : 3; + sel.MediaSamplerDOPClockGateEnable = GFX_VER >= 12; #endif sel.PipelineSelection = pipeline; } @@ -677,7 +677,7 @@ emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline) UNUSED static void init_glk_barrier_mode(struct iris_batch *batch, uint32_t value) { -#if GEN_GEN == 9 +#if GFX_VER == 9 /* Project: DevGLK * * "This chicken bit works around a hardware issue with barrier @@ -720,7 +720,7 @@ init_state_base_address(struct iris_batch *batch) sba.InstructionBaseAddressModifyEnable = true; sba.GeneralStateBufferSizeModifyEnable = true; sba.DynamicStateBufferSizeModifyEnable = true; -#if (GEN_GEN >= 9) +#if (GFX_VER >= 9) sba.BindlessSurfaceStateBaseAddressModifyEnable = true; sba.BindlessSurfaceStateMOCS = mocs; #endif @@ -743,9 +743,9 @@ static void iris_emit_l3_config(struct iris_batch *batch, const struct intel_l3_config *cfg) { - assert(cfg || GEN_GEN >= 12); + assert(cfg || GFX_VER >= 12); -#if GEN_GEN >= 12 +#if GFX_VER >= 12 #define L3_ALLOCATION_REG GENX(L3ALLOC) #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num) #else @@ -754,10 +754,10 @@ iris_emit_l3_config(struct iris_batch *batch, #endif iris_emit_reg(batch, L3_ALLOCATION_REG, reg) { -#if GEN_GEN < 11 +#if GFX_VER < 11 reg.SLMEnable = cfg->n[INTEL_L3P_SLM] > 0; #endif -#if GEN_GEN == 11 +#if GFX_VER == 11 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set * in L3CNTLREG register. The default setting of the bit is not the * desirable behavior. @@ -765,20 +765,20 @@ iris_emit_l3_config(struct iris_batch *batch, reg.ErrorDetectionBehaviorControl = true; reg.UseFullWays = true; #endif - if (GEN_GEN < 12 || cfg) { + if (GFX_VER < 12 || cfg) { reg.URBAllocation = cfg->n[INTEL_L3P_URB]; reg.ROAllocation = cfg->n[INTEL_L3P_RO]; reg.DCAllocation = cfg->n[INTEL_L3P_DC]; reg.AllAllocation = cfg->n[INTEL_L3P_ALL]; } else { -#if GEN_GEN >= 12 +#if GFX_VER >= 12 reg.L3FullWayAllocationEnable = true; #endif } } } -#if GEN_GEN == 9 +#if GFX_VER == 9 static void iris_enable_obj_preemption(struct iris_batch *batch, bool enable) { @@ -834,7 +834,7 @@ calculate_pixel_hashing_table(unsigned n, unsigned m, } } -#if GEN_GEN == 11 +#if GFX_VER == 11 static void gen11_upload_pixel_hashing_tables(struct iris_batch *batch) { @@ -941,7 +941,7 @@ iris_alloc_push_constants(struct iris_batch *batch) } } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 static void init_aux_map_state(struct iris_batch *batch); #endif @@ -954,7 +954,7 @@ init_aux_map_state(struct iris_batch *batch); static void iris_init_common_context(struct iris_batch *batch) { -#if GEN_GEN == 11 +#if GFX_VER == 11 iris_emit_reg(batch, GENX(SAMPLER_MODE), reg) { reg.HeaderlessMessageforPreemptableContexts = 1; reg.HeaderlessMessageforPreemptableContextsMask = 1; @@ -989,7 +989,7 @@ iris_init_render_context(struct iris_batch *batch) iris_init_common_context(batch); -#if GEN_GEN >= 9 +#if GFX_VER >= 9 iris_emit_reg(batch, GENX(CS_DEBUG_MODE2), reg) { reg.CONSTANT_BUFFERAddressOffsetDisable = true; reg.CONSTANT_BUFFERAddressOffsetDisableMask = true; @@ -1001,7 +1001,7 @@ iris_init_render_context(struct iris_batch *batch) } #endif -#if GEN_GEN == 9 +#if GFX_VER == 9 iris_emit_reg(batch, GENX(CACHE_MODE_1), reg) { reg.FloatBlendOptimizationEnable = true; reg.FloatBlendOptimizationEnableMask = true; @@ -1015,7 +1015,7 @@ iris_init_render_context(struct iris_batch *batch) init_glk_barrier_mode(batch, GLK_BARRIER_MODE_3D_HULL); #endif -#if GEN_GEN == 11 +#if GFX_VER == 11 iris_emit_reg(batch, GENX(TCCNTLREG), reg) { reg.L3DataPartialWriteMergingEnable = true; reg.ColorZPartialWriteMergingEnable = true; @@ -1056,7 +1056,7 @@ iris_init_render_context(struct iris_batch *batch) INTEL_SAMPLE_POS_2X(pat._2xSample); INTEL_SAMPLE_POS_4X(pat._4xSample); INTEL_SAMPLE_POS_8X(pat._8xSample); -#if GEN_GEN >= 9 +#if GFX_VER >= 9 INTEL_SAMPLE_POS_16X(pat._16xSample); #endif } @@ -1077,7 +1077,7 @@ iris_init_render_context(struct iris_batch *batch) iris_alloc_push_constants(batch); -#if GEN_GEN >= 12 +#if GFX_VER >= 12 init_aux_map_state(batch); #endif @@ -1095,7 +1095,7 @@ iris_init_compute_context(struct iris_batch *batch) * * Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS. */ -#if GEN_GEN == 12 +#if GFX_VER == 12 emit_pipeline_select(batch, _3D); #else emit_pipeline_select(batch, GPGPU); @@ -1107,16 +1107,16 @@ iris_init_compute_context(struct iris_batch *batch) iris_init_common_context(batch); -#if GEN_GEN == 12 +#if GFX_VER == 12 emit_pipeline_select(batch, GPGPU); #endif -#if GEN_GEN == 9 +#if GFX_VER == 9 if (devinfo->is_geminilake) init_glk_barrier_mode(batch, GLK_BARRIER_MODE_GPGPU); #endif -#if GEN_GEN >= 12 +#if GFX_VER >= 12 init_aux_map_state(batch); #endif @@ -1156,17 +1156,17 @@ struct iris_genx_state { uint32_t so_buffers[4 * GENX(3DSTATE_SO_BUFFER_length)]; -#if GEN_GEN == 8 +#if GFX_VER == 8 bool pma_fix_enabled; #endif -#if GEN_GEN == 9 +#if GFX_VER == 9 /* Is object level preemption enabled? */ bool object_preemption; #endif struct { -#if GEN_GEN == 8 +#if GFX_VER == 8 struct brw_image_param image_param[PIPE_MAX_SHADER_IMAGES]; #endif } shaders[MESA_SHADER_STAGES]; @@ -1346,7 +1346,7 @@ iris_bind_blend_state(struct pipe_context *ctx, void *state) ice->state.dirty |= IRIS_DIRTY_BLEND_STATE; ice->state.stage_dirty |= ice->state.stage_dirty_for_nos[IRIS_NOS_BLEND]; - if (GEN_GEN == 8) + if (GFX_VER == 8) ice->state.dirty |= IRIS_DIRTY_PMA_FIX; } @@ -1376,7 +1376,7 @@ struct iris_depth_stencil_alpha_state { /** Partial 3DSTATE_WM_DEPTH_STENCIL. */ uint32_t wmds[GENX(3DSTATE_WM_DEPTH_STENCIL_length)]; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 uint32_t depth_bounds[GENX(3DSTATE_DEPTH_BOUNDS_length)]; #endif @@ -1444,12 +1444,12 @@ iris_create_zsa_state(struct pipe_context *ctx, wmds.BackfaceStencilTestMask = state->stencil[1].valuemask; wmds.BackfaceStencilWriteMask = state->stencil[1].writemask; /* wmds.[Backface]StencilReferenceValue are merged later */ -#if GEN_GEN >= 12 +#if GFX_VER >= 12 wmds.StencilReferenceValueModifyDisable = true; #endif } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 iris_pack_command(GENX(3DSTATE_DEPTH_BOUNDS), cso->depth_bounds, depth_bounds) { depth_bounds.DepthBoundsTestValueModifyDisable = false; depth_bounds.DepthBoundsTestEnableModifyDisable = false; @@ -1490,7 +1490,7 @@ iris_bind_zsa_state(struct pipe_context *ctx, void *state) ice->state.depth_writes_enabled = new_cso->depth_writes_enabled; ice->state.stencil_writes_enabled = new_cso->stencil_writes_enabled; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 if (cso_changed(depth_bounds)) ice->state.dirty |= IRIS_DIRTY_DEPTH_BOUNDS; #endif @@ -1502,11 +1502,11 @@ iris_bind_zsa_state(struct pipe_context *ctx, void *state) ice->state.stage_dirty |= ice->state.stage_dirty_for_nos[IRIS_NOS_DEPTH_STENCIL_ALPHA]; - if (GEN_GEN == 8) + if (GFX_VER == 8) ice->state.dirty |= IRIS_DIRTY_PMA_FIX; } -#if GEN_GEN == 8 +#if GFX_VER == 8 static bool want_pma_fix(struct iris_context *ice) { @@ -1634,7 +1634,7 @@ genX(update_pma_fix)(struct iris_context *ice, struct iris_batch *batch, bool enable) { -#if GEN_GEN == 8 +#if GFX_VER == 8 struct iris_genx_state *genx = ice->state.genx; if (genx->pma_fix_enabled == enable) @@ -1819,7 +1819,7 @@ iris_create_rasterizer_state(struct pipe_context *ctx, rr.SmoothPointEnable = state->point_smooth; rr.AntialiasingEnable = state->line_smooth; rr.ScissorRectangleEnable = state->scissor; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 rr.ViewportZNearClipTestEnable = state->depth_clip_near; rr.ViewportZFarClipTestEnable = state->depth_clip_far; rr.ConservativeRasterizationEnable = @@ -2026,7 +2026,7 @@ iris_create_sampler_state(struct pipe_context *ctx, if (state->compare_mode == PIPE_TEX_COMPARE_R_TO_TEXTURE) samp.ShadowFunction = translate_shadow_func(state->compare_func); - const float hw_max_lod = GEN_GEN >= 7 ? 14 : 13; + const float hw_max_lod = GFX_VER >= 7 ? 14 : 13; samp.LODPreClampMode = CLAMP_MODE_OGL; samp.MinLOD = CLAMP(min_lod, 0, hw_max_lod); @@ -2304,7 +2304,7 @@ update_surface_state_addrs(struct u_upload_mgr *mgr, return true; } -#if GEN_GEN == 8 +#if GFX_VER == 8 /** * Return an ISL surface for use with non-coherent render target reads. * @@ -2573,7 +2573,7 @@ iris_create_surface(struct pipe_context *ctx, .usage = usage, }; -#if GEN_GEN == 8 +#if GFX_VER == 8 enum pipe_texture_target target = (tex->target == PIPE_TEXTURE_3D && array_len == 1) ? PIPE_TEXTURE_2D : tex->target == PIPE_TEXTURE_1D_ARRAY ? @@ -2602,7 +2602,7 @@ iris_create_surface(struct pipe_context *ctx, alloc_surface_states(&surf->surface_state, res->aux.possible_usages); surf->surface_state.bo_address = res->bo->gtt_offset; -#if GEN_GEN == 8 +#if GFX_VER == 8 alloc_surface_states(&surf->surface_state_read, res->aux.possible_usages); surf->surface_state_read.bo_address = res->bo->gtt_offset; #endif @@ -2624,7 +2624,7 @@ iris_create_surface(struct pipe_context *ctx, view, aux_usage, 0, 0, 0); map += SURFACE_STATE_ALIGNMENT; -#if GEN_GEN == 8 +#if GFX_VER == 8 struct isl_surf surf; uint32_t offset_to_tile = 0, tile_x_sa = 0, tile_y_sa = 0; get_rt_read_isl_surf(devinfo, res, target, read_view, @@ -2668,7 +2668,7 @@ iris_create_surface(struct pipe_context *ctx, * * Return NULL to force gallium frontends to take fallback paths. */ - if (view->array_len > 1 || GEN_GEN == 8) + if (view->array_len > 1 || GFX_VER == 8) return NULL; const bool is_3d = res->surf.dim == ISL_SURF_DIM_3D; @@ -2719,7 +2719,7 @@ iris_create_surface(struct pipe_context *ctx, return psurf; } -#if GEN_GEN < 9 +#if GFX_VER < 9 static void fill_default_image_param(struct brw_image_param *param) { @@ -2763,7 +2763,7 @@ iris_set_shader_images(struct pipe_context *ctx, struct iris_screen *screen = (struct iris_screen *)ctx->screen; gl_shader_stage stage = stage_from_pipe(p_stage); struct iris_shader_state *shs = &ice->state.shaders[stage]; -#if GEN_GEN == 8 +#if GFX_VER == 8 struct iris_genx_state *genx = ice->state.genx; struct brw_image_param *image_params = genx->shaders[stage].image_param; #endif @@ -2788,7 +2788,7 @@ iris_set_shader_images(struct pipe_context *ctx, enum isl_format isl_fmt = iris_image_view_get_format(ice, img); /* Render compression with images supported on gen12+ only. */ - unsigned aux_usages = GEN_GEN >= 12 ? res->aux.possible_usages : + unsigned aux_usages = GFX_VER >= 12 ? res->aux.possible_usages : 1 << ISL_AUX_USAGE_NONE; alloc_surface_states(&iv->surface_state, aux_usages); @@ -2854,7 +2854,7 @@ iris_set_shader_images(struct pipe_context *ctx, : IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES; /* Broadwell also needs brw_image_params re-uploaded */ - if (GEN_GEN < 9) { + if (GFX_VER < 9) { ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_VS << stage; shs->sysvals_need_upload = true; } @@ -3065,9 +3065,9 @@ iris_set_stencil_ref(struct pipe_context *ctx, { struct iris_context *ice = (struct iris_context *) ctx; memcpy(&ice->state.stencil_ref, &state, sizeof(state)); - if (GEN_GEN >= 12) + if (GFX_VER >= 12) ice->state.dirty |= IRIS_DIRTY_STENCIL_REF; - else if (GEN_GEN >= 9) + else if (GFX_VER >= 9) ice->state.dirty |= IRIS_DIRTY_WM_DEPTH_STENCIL; else ice->state.dirty |= IRIS_DIRTY_COLOR_CALC_STATE; @@ -3127,7 +3127,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx, ice->state.dirty |= IRIS_DIRTY_MULTISAMPLE; /* We need to toggle 3DSTATE_PS::32 Pixel Dispatch Enable */ - if (GEN_GEN >= 9 && (cso->samples == 16 || samples == 16)) + if (GFX_VER >= 9 && (cso->samples == 16 || samples == 16)) ice->state.stage_dirty |= IRIS_STAGE_DIRTY_FS; } @@ -3225,7 +3225,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx, ice->state.stage_dirty |= ice->state.stage_dirty_for_nos[IRIS_NOS_FRAMEBUFFER]; - if (GEN_GEN == 8) + if (GFX_VER == 8) ice->state.dirty |= IRIS_DIRTY_PMA_FIX; } @@ -3328,7 +3328,7 @@ upload_sysvals(struct iris_context *ice, uint32_t value = 0; if (BRW_PARAM_DOMAIN(sysval) == BRW_PARAM_DOMAIN_IMAGE) { -#if GEN_GEN == 8 +#if GFX_VER == 8 unsigned img = BRW_PARAM_IMAGE_IDX(sysval); unsigned offset = BRW_PARAM_IMAGE_OFFSET(sysval); struct brw_image_param *param = @@ -3770,7 +3770,7 @@ iris_set_stream_output_targets(struct pipe_context *ctx, if (!tgt) { iris_pack_command(GENX(3DSTATE_SO_BUFFER), so_buffers, sob) { -#if GEN_GEN < 12 +#if GFX_VER < 12 sob.SOBufferIndex = i; #else sob._3DCommandOpcode = 0; @@ -3805,7 +3805,7 @@ iris_set_stream_output_targets(struct pipe_context *ctx, tgt->zero_offset = true; iris_pack_command(GENX(3DSTATE_SO_BUFFER), so_buffers, sob) { -#if GEN_GEN < 12 +#if GFX_VER < 12 sob.SOBufferIndex = i; #else sob._3DCommandOpcode = 0; @@ -4198,7 +4198,7 @@ iris_emit_sbe(struct iris_batch *batch, const struct iris_context *ice) sbe.ForceVertexURBEntryReadLength = true; sbe.ConstantInterpolationEnable = wm_prog_data->flat_inputs; sbe.PointSpriteTextureCoordinateEnable = sprite_coord_overrides; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 for (int i = 0; i < 32; i++) { sbe.AttributeActiveComponentFormat[i] = ACTIVE_COMPONENT_XYZW; } @@ -4299,7 +4299,7 @@ iris_populate_fs_key(const struct iris_context *ice, key->persample_interp = rast->force_persample_interp; key->multisample_fbo = rast->multisample && fb->samples > 1; - key->coherent_fb_fetch = GEN_GEN >= 9; + key->coherent_fb_fetch = GFX_VER >= 9; key->force_dual_color_blend = screen->driconf.dual_color_blend_by_location && @@ -4382,7 +4382,7 @@ iris_store_tcs_state(const struct gen_device_info *devinfo, iris_pack_command(GENX(3DSTATE_HS), shader->derived_data, hs) { INIT_THREAD_DISPATCH_FIELDS(hs, Vertex, MESA_SHADER_TESS_CTRL); -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* GEN:BUG:1604578095: * * Hang occurs when the number of max threads is less than 2 times @@ -4398,14 +4398,14 @@ iris_store_tcs_state(const struct gen_device_info *devinfo, hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1; hs.IncludeVertexHandles = true; -#if GEN_GEN == 12 +#if GFX_VER == 12 /* Patch Count threshold specifies the maximum number of patches that * will be accumulated before a thread dispatch is forced. */ hs.PatchCountThreshold = tcs_prog_data->patch_count_threshold; #endif -#if GEN_GEN >= 9 +#if GFX_VER >= 9 hs.DispatchMode = vue_prog_data->dispatch_mode; hs.IncludePrimitiveID = tcs_prog_data->include_primitive_id; #endif @@ -4474,7 +4474,7 @@ iris_store_gs_state(const struct gen_device_info *devinfo, gs.ReorderMode = TRAILING; gs.ExpectedVertexCount = gs_prog_data->vertices_in; gs.MaximumNumberofThreads = - GEN_GEN == 8 ? (devinfo->max_gs_threads / 2 - 1) + GFX_VER == 8 ? (devinfo->max_gs_threads / 2 - 1) : (devinfo->max_gs_threads - 1); if (gs_prog_data->static_vertex_count != -1) { @@ -4513,7 +4513,7 @@ iris_store_fs_state(const struct gen_device_info *devinfo, ps.VectorMaskEnable = true; ps.BindingTableEntryCount = shader->bt.size_bytes / 4; ps.FloatingPointMode = prog_data->use_alt_mode; - ps.MaximumNumberofThreadsPerPSD = 64 - (GEN_GEN == 8 ? 2 : 1); + ps.MaximumNumberofThreadsPerPSD = 64 - (GFX_VER == 8 ? 2 : 1); ps.PushConstantEnable = prog_data->ubo_ranges[0].length > 0; @@ -4547,7 +4547,7 @@ iris_store_fs_state(const struct gen_device_info *devinfo, psx.PixelShaderIsPerSample = wm_prog_data->persample_dispatch; psx.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 psx.PixelShaderPullsBary = wm_prog_data->pulls_bary; psx.PixelShaderComputesStencil = wm_prog_data->computed_stencil; #endif @@ -4576,7 +4576,7 @@ iris_store_cs_state(const struct gen_device_info *devinfo, assert(cs_prog_data->push.cross_thread.regs == 0); #endif desc.BarrierEnable = cs_prog_data->uses_barrier; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* TODO: Check if we are missing workarounds and enable mid-thread * preemption. * @@ -4691,7 +4691,7 @@ surf_state_offset_for_aux(struct iris_resource *res, util_bitcount(aux_modes & ((1 << aux_usage) - 1)); } -#if GEN_GEN == 9 +#if GFX_VER == 9 static void surf_state_update_clear_value(struct iris_batch *batch, struct iris_resource *res, @@ -4748,7 +4748,7 @@ update_clear_value(struct iris_context *ice, /* We only need to update the clear color in the surface state for gen8 and * gen9. Newer gens can read it directly from the clear color state buffer. */ -#if GEN_GEN == 9 +#if GFX_VER == 9 /* Skip updating the ISL_AUX_USAGE_NONE surface state */ aux_modes &= ~(1 << ISL_AUX_USAGE_NONE); @@ -4758,7 +4758,7 @@ update_clear_value(struct iris_context *ice, surf_state_update_clear_value(batch, res, &surf_state->ref, all_aux_modes, aux_usage); } -#elif GEN_GEN == 8 +#elif GFX_VER == 8 /* TODO: Could update rather than re-filling */ alloc_surface_states(surf_state, all_aux_modes); @@ -4794,7 +4794,7 @@ use_surface(struct iris_context *ice, struct iris_resource *res = (void *) p_surf->texture; uint32_t offset = 0; - if (GEN_GEN == 8 && is_read_surface && !surf->surface_state_read.ref.res) { + if (GFX_VER == 8 && is_read_surface && !surf->surface_state_read.ref.res) { upload_surface_states(ice->state.surface_uploader, &surf->surface_state_read); } @@ -4813,7 +4813,7 @@ use_surface(struct iris_context *ice, sizeof(surf->clear_color)) != 0) { update_clear_value(ice, batch, res, &surf->surface_state, res->aux.possible_usages, &surf->view); - if (GEN_GEN == 8) { + if (GFX_VER == 8) { update_clear_value(ice, batch, res, &surf->surface_state_read, res->aux.possible_usages, &surf->read_view); } @@ -4823,7 +4823,7 @@ use_surface(struct iris_context *ice, iris_use_pinned_bo(batch, iris_resource_bo(p_surf->texture), writeable, access); - if (GEN_GEN == 8 && is_read_surface) { + if (GFX_VER == 8 && is_read_surface) { iris_use_pinned_bo(batch, iris_resource_bo(surf->surface_state_read.ref.res), false, IRIS_DOMAIN_NONE); } else { @@ -4831,7 +4831,7 @@ use_surface(struct iris_context *ice, IRIS_DOMAIN_NONE); } - offset = (GEN_GEN == 8 && is_read_surface) + offset = (GFX_VER == 8 && is_read_surface) ? surf->surface_state_read.ref.offset : surf->surface_state.ref.offset; @@ -4986,7 +4986,7 @@ iris_populate_binding_table(struct iris_context *ice, } push_bt_entry(addr); } - } else if (GEN_GEN < 11) { + } else if (GFX_VER < 11) { uint32_t addr = use_null_fb_surface(batch, ice); push_bt_entry(addr); } @@ -5311,7 +5311,7 @@ iris_update_surface_base_address(struct iris_batch *batch, flush_before_state_base_change(batch); -#if GEN_GEN == 12 +#if GFX_VER == 12 /* GEN:BUG:1607854226: * * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline @@ -5334,12 +5334,12 @@ iris_update_surface_base_address(struct iris_batch *batch, sba.IndirectObjectMOCS = mocs; sba.InstructionMOCS = mocs; sba.SurfaceStateMOCS = mocs; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 sba.BindlessSurfaceStateMOCS = mocs; #endif } -#if GEN_GEN == 12 +#if GFX_VER == 12 /* GEN:BUG:1607854226: * * Put the pipeline back into compute mode. @@ -5366,7 +5366,7 @@ iris_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz, util_viewport_zmin_zmax(vp, halfz, zmin, zmax); } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 void genX(invalidate_aux_map_state)(struct iris_batch *batch) { @@ -5485,7 +5485,7 @@ emit_push_constant_packets(struct iris_context *ice, iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) { pkt._3DCommandSubOpcode = push_constant_opcodes[stage]; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pkt.MOCS = isl_mocs(isl_dev, 0, false); #endif if (prog_data) { @@ -5512,7 +5512,7 @@ emit_push_constant_packets(struct iris_context *ice, } } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 static void emit_push_constant_packet_all(struct iris_context *ice, struct iris_batch *batch, @@ -5720,7 +5720,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, if (dirty & IRIS_DIRTY_COLOR_CALC_STATE) { struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa; -#if GEN_GEN == 8 +#if GFX_VER == 8 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref; #endif uint32_t cc_offset; @@ -5736,7 +5736,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, cc.BlendConstantColorGreen = ice->state.blend_color.color[1]; cc.BlendConstantColorBlue = ice->state.blend_color.color[2]; cc.BlendConstantColorAlpha = ice->state.blend_color.color[3]; -#if GEN_GEN == 8 +#if GFX_VER == 8 cc.StencilReferenceValue = p_stencil_refs->ref_value[0]; cc.BackfaceStencilReferenceValue = p_stencil_refs->ref_value[1]; #endif @@ -5754,11 +5754,11 @@ iris_upload_dirty_render_state(struct iris_context *ice, * Testing shows that all the 3DSTATE_CONSTANT_XS need to be emitted if * any stage has a dirty binding table. */ - const bool emit_const_wa = GEN_GEN >= 11 && + const bool emit_const_wa = GFX_VER >= 11 && ((dirty & IRIS_DIRTY_RENDER_BUFFER) || (stage_dirty & IRIS_ALL_STAGE_DIRTY_BINDINGS)); -#if GEN_GEN >= 12 +#if GFX_VER >= 12 uint32_t nobuffer_stages = 0; #endif @@ -5779,7 +5779,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, struct push_bos push_bos = {}; setup_constant_buffers(ice, batch, stage, &push_bos); -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* If this stage doesn't have any push constants, emit it later in a * single CONSTANT_ALL packet with all the other stages. */ @@ -5800,7 +5800,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, emit_push_constant_packets(ice, batch, stage, &push_bos); } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 if (nobuffer_stages) emit_push_constant_packet_all(ice, batch, nobuffer_stages, NULL); #endif @@ -5811,7 +5811,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, * at Set Shader" to go back to legacy mode... */ if (stage_dirty & ((IRIS_STAGE_DIRTY_BINDINGS_VS | - (GEN_GEN == 9 ? IRIS_STAGE_DIRTY_CONSTANTS_VS : 0)) + (GFX_VER == 9 ? IRIS_STAGE_DIRTY_CONSTANTS_VS : 0)) << stage)) { iris_emit_cmd(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), ptr) { ptr._3DCommandSubOpcode = 38 + stage; @@ -5820,7 +5820,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, } } - if (GEN_GEN >= 11 && (dirty & IRIS_DIRTY_RENDER_BUFFER)) { + if (GFX_VER >= 11 && (dirty & IRIS_DIRTY_RENDER_BUFFER)) { // XXX: we may want to flag IRIS_DIRTY_MULTISAMPLE (or SAMPLE_MASK?) // XXX: see commit 979fc1bc9bcc64027ff2cfafd285676f31b930a6 @@ -5914,7 +5914,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, * * 16x MSAA only exists on Gen9+, so we can skip this on Gen8. */ - if (GEN_GEN >= 9 && cso_fb->samples == 16 && + if (GFX_VER >= 9 && cso_fb->samples == 16 && !wm_prog_data->persample_dispatch) { assert(ps._8PixelDispatchEnable || ps._16PixelDispatchEnable); ps._32PixelDispatchEnable = false; @@ -5940,7 +5940,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, uint32_t psx_state[GENX(3DSTATE_PS_EXTRA_length)] = {0}; iris_pack_command(GENX(3DSTATE_PS_EXTRA), psx_state, psx) { -#if GEN_GEN >= 9 +#if GFX_VER >= 9 if (!wm_prog_data->uses_sample_mask) psx.InputCoverageMaskState = ICMS_NONE; else if (wm_prog_data->post_depth_coverage) @@ -6090,7 +6090,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, iris_pack_command(GENX(3DSTATE_SF), &dynamic_sf, sf) { sf.ViewportTransformEnable = !ice->state.window_space_position; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 sf.DerefBlockSize = ice->state.urb_deref_block_size; #endif } @@ -6150,7 +6150,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) { struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa; -#if GEN_GEN >= 9 && GEN_GEN < 12 +#if GFX_VER >= 9 && GFX_VER < 12 struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref; uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)]; iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) { @@ -6165,13 +6165,13 @@ iris_upload_dirty_render_state(struct iris_context *ice, iris_batch_emit(batch, cso->wmds, sizeof(cso->wmds)); #endif -#if GEN_GEN >= 12 +#if GFX_VER >= 12 iris_batch_emit(batch, cso->depth_bounds, sizeof(cso->depth_bounds)); #endif } if (dirty & IRIS_DIRTY_STENCIL_REF) { -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* Use modify disable fields which allow us to emit packets * directly instead of merging them later. */ @@ -6218,7 +6218,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4; uint32_t cso_z_size = batch->screen->isl_dev.ds.size - clear_length;; -#if GEN_GEN == 12 +#if GFX_VER == 12 /* GEN:BUG:14010455700 * * ISL will change some CHICKEN registers depending on the depth surface @@ -6233,7 +6233,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, #endif iris_batch_emit(batch, cso_z->packets, cso_z_size); - if (GEN_GEN >= 12) { + if (GFX_VER >= 12) { /* GEN:BUG:1408224581 * * Workaround: Gen12LP Astep only An additional pipe control with @@ -6343,7 +6343,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, } if (count) { -#if GEN_GEN >= 11 +#if GFX_VER >= 11 /* Gen11+ doesn't need the cache workaround below */ uint64_t bound = dynamic_bound; while (bound) { @@ -6534,7 +6534,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, } } -#if GEN_GEN == 8 +#if GFX_VER == 8 if (dirty & IRIS_DIRTY_PMA_FIX) { bool enable = want_pma_fix(ice); genX(update_pma_fix)(ice, batch, enable); @@ -6544,7 +6544,7 @@ iris_upload_dirty_render_state(struct iris_context *ice, if (ice->state.current_hash_scale != 1) genX(emit_hashing_mode)(ice, batch, UINT_MAX, UINT_MAX, 1); -#if GEN_GEN >= 12 +#if GFX_VER >= 12 genX(invalidate_aux_map_state)(batch); #endif } @@ -6613,7 +6613,7 @@ iris_upload_render_state(struct iris_context *ice, iris_use_pinned_bo(batch, bo, false, IRIS_DOMAIN_OTHER_READ); } -#if GEN_GEN < 11 +#if GFX_VER < 11 /* The VF cache key only uses 32-bits, see vertex buffer comment above */ uint16_t high_bits = bo->gtt_offset >> 32ull; if (high_bits != ice->state.last_index_bo_high_bits) { @@ -6852,7 +6852,7 @@ iris_upload_compute_walker(struct iris_context *ice, .KernelStartPointer = KSP(shader), .NumberofThreadsinGPGPUThreadGroup = threads, .SharedLocalMemorySize = - encode_slm_size(GEN_GEN, prog_data->total_shared), + encode_slm_size(GFX_VER, prog_data->total_shared), .BarrierEnable = cs_prog_data->uses_barrier, .SamplerStatePointer = shs->sampler_table.offset, .BindingTablePointer = binder->bt_offset[MESA_SHADER_COMPUTE], @@ -6912,11 +6912,11 @@ iris_upload_gpgpu_walker(struct iris_context *ice, vfe.MaximumNumberofThreads = devinfo->max_cs_threads * screen->subslice_total - 1; -#if GEN_GEN < 11 +#if GFX_VER < 11 vfe.ResetGatewayTimer = Resettingrelativetimerandlatchingtheglobaltimestamp; #endif -#if GEN_GEN == 8 +#if GFX_VER == 8 vfe.BypassGatewayControl = true; #endif vfe.NumberofURBEntries = 2; @@ -6969,7 +6969,7 @@ iris_upload_gpgpu_walker(struct iris_context *ice, iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA), desc, idd) { idd.SharedLocalMemorySize = - encode_slm_size(GEN_GEN, ish->kernel_shared_size); + encode_slm_size(GFX_VER, ish->kernel_shared_size); idd.KernelStartPointer = KSP(shader) + brw_cs_prog_data_prog_offset(cs_prog_data, simd_size); idd.SamplerStatePointer = shs->sampler_table.offset; @@ -7053,7 +7053,7 @@ iris_upload_compute_state(struct iris_context *ice, iris_use_pinned_bo(batch, ice->state.border_color_pool.bo, false, IRIS_DOMAIN_NONE); -#if GEN_GEN >= 12 +#if GFX_VER >= 12 genX(invalidate_aux_map_state)(batch); #endif @@ -7384,7 +7384,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, * We do these first because we want to look at the original operation, * rather than any workarounds we set. */ - if (GEN_GEN == 9 && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) { + if (GFX_VER == 9 && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) { /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description * lists several workarounds: * @@ -7404,7 +7404,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which * invalidates the instruction cache */ - if (GEN_GEN == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) { + if (GFX_VER == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) { iris_emit_raw_pipe_control(batch, "workaround: CS stall before instruction " "cache invalidate", @@ -7413,7 +7413,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, imm); } - if ((GEN_GEN == 9 || (GEN_GEN == 12 && devinfo->revision == 0 /* A0*/)) && + if ((GFX_VER == 9 || (GFX_VER == 12 && devinfo->revision == 0 /* A0*/)) && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) { /* Project: SKL / Argument: LRI Post Sync Operation [23] * @@ -7435,7 +7435,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, * We do these now because they may add post-sync operations or CS stalls. */ - if (GEN_GEN < 11 && flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) { + if (GFX_VER < 11 && flags & PIPE_CONTROL_VF_CACHE_INVALIDATE) { /* Project: BDW, SKL+ (stopping at CNL) / Argument: VF Invalidate * * "'Post Sync Operation' must be enabled to 'Write Immediate Data' or @@ -7479,7 +7479,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, PIPE_CONTROL_WRITE_TIMESTAMP))); } - if (GEN_GEN < 11 && (flags & PIPE_CONTROL_STALL_AT_SCOREBOARD)) { + if (GFX_VER < 11 && (flags & PIPE_CONTROL_STALL_AT_SCOREBOARD)) { /* From the PIPE_CONTROL instruction table, bit 1: * * "This bit is ignored if Depth Stall Enable is set. @@ -7499,7 +7499,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, /* PIPE_CONTROL page workarounds ------------------------------------- */ - if (GEN_GEN <= 8 && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) { + if (GFX_VER <= 8 && (flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE)) { /* From the PIPE_CONTROL page itself: * * "IVB, HSW, BDW @@ -7597,7 +7597,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, flags |= PIPE_CONTROL_CS_STALL; } - if (GEN_GEN >= 12 && ((flags & PIPE_CONTROL_RENDER_TARGET_FLUSH) || + if (GFX_VER >= 12 && ((flags & PIPE_CONTROL_RENDER_TARGET_FLUSH) || (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH))) { /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush * Enable): @@ -7614,21 +7614,21 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; } - if (GEN_GEN == 9 && devinfo->gt == 4) { + if (GFX_VER == 9 && devinfo->gt == 4) { /* TODO: The big Skylake GT4 post sync op workaround */ } /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */ if (IS_COMPUTE_PIPELINE(batch)) { - if (GEN_GEN >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { + if (GFX_VER >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { /* Project: SKL+ / Argument: Tex Invalidate * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." */ flags |= PIPE_CONTROL_CS_STALL; } - if (GEN_GEN == 8 && (post_sync_flags || + if (GFX_VER == 8 && (post_sync_flags || (flags & (PIPE_CONTROL_NOTIFY_ENABLE | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_RENDER_TARGET_FLUSH | @@ -7673,7 +7673,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, * some additional CS stalls above. */ - if (GEN_GEN < 9 && (flags & PIPE_CONTROL_CS_STALL)) { + if (GFX_VER < 9 && (flags & PIPE_CONTROL_CS_STALL)) { /* Project: PRE-SKL, VLV, CHV * * "[All Stepping][All SKUs]: @@ -7705,7 +7705,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; } - if (GEN_GEN >= 12 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) { + if (GFX_VER >= 12 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) { /* GEN:BUG:1409600907: * * "PIPE_CONTROL with Depth Stall Enable bit must be set @@ -7749,10 +7749,10 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, iris_batch_sync_region_start(batch); iris_emit_cmd(batch, GENX(PIPE_CONTROL), pc) { -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pc.TileCacheFlushEnable = flags & PIPE_CONTROL_TILE_CACHE_FLUSH; #endif -#if GEN_GEN >= 11 +#if GFX_VER >= 11 pc.HDCPipelineFlushEnable = flags & PIPE_CONTROL_FLUSH_HDC; #endif pc.LRIPostSyncOperation = NoLRIOperation; @@ -7789,7 +7789,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, iris_batch_sync_region_end(batch); } -#if GEN_GEN == 9 +#if GFX_VER == 9 /** * Preemption on Gen9 has to be enabled or disabled in various cases. * @@ -7901,7 +7901,7 @@ void genX(emit_hashing_mode)(struct iris_context *ice, struct iris_batch *batch, unsigned width, unsigned height, unsigned scale) { -#if GEN_GEN == 9 +#if GFX_VER == 9 const struct gen_device_info *devinfo = &batch->screen->devinfo; const unsigned slice_hashing[] = { /* Because all Gen9 platforms with more than one slice require diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index fd4bd988800..eaa9717fa4e 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -90,12 +90,12 @@ static uint64_t blorp_get_surface_address(struct blorp_batch *batch, struct blorp_address address); -#if GEN_GEN >= 7 && GEN_GEN < 10 +#if GFX_VER >= 7 && GFX_VER < 10 static struct blorp_address blorp_get_surface_base_address(struct blorp_batch *batch); #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static const struct intel_l3_config * blorp_get_l3_config(struct blorp_batch *batch); # else @@ -216,7 +216,7 @@ emit_urb_config(struct blorp_batch *batch, ASSERTED const unsigned sf_entry_size = params->sf_prog_data ? params->sf_prog_data->urb_entry_size : 0; -#if GEN_GEN >= 7 +#if GFX_VER >= 7 assert(sf_entry_size == 0); const unsigned entry_size[4] = { vs_entry_size, 1, 1, 1 }; @@ -251,12 +251,12 @@ emit_urb_config(struct blorp_batch *batch, urb.VSNumberofURBEntries = entries[i]; } } -#else /* GEN_GEN < 7 */ +#else /* GFX_VER < 7 */ blorp_emit_urb_config(batch, vs_entry_size, sf_entry_size); #endif } -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void blorp_emit_memcpy(struct blorp_batch *batch, struct blorp_address dst, @@ -326,7 +326,7 @@ blorp_emit_input_varying_data(struct blorp_batch *batch, blorp_flush_range(batch, data, *size); if (params->dst_clear_color_as_input) { -#if GEN_GEN >= 7 +#if GFX_VER >= 7 /* In this case, the clear color isn't known statically and instead * comes in through an indirect which we have to copy into the vertex * buffer before we execute the 3DPRIMITIVE. We already copied the @@ -341,7 +341,7 @@ blorp_emit_input_varying_data(struct blorp_batch *batch, clear_color_input_addr.offset += 16; const unsigned clear_color_size = - GEN_GEN < 10 ? batch->blorp->isl_dev->ss.clear_value_size : 4 * 4; + GFX_VER < 10 ? batch->blorp->isl_dev->ss.clear_value_size : 4 * 4; blorp_emit_memcpy(batch, clear_color_input_addr, params->dst.clear_color_addr, clear_color_size); @@ -361,21 +361,21 @@ blorp_fill_vertex_buffer_state(struct GENX(VERTEX_BUFFER_STATE) *vb, vb[idx].BufferStartingAddress = addr; vb[idx].BufferPitch = stride; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 vb[idx].MOCS = addr.mocs; #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 vb[idx].AddressModifyEnable = true; #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 vb[idx].BufferSize = size; -#elif GEN_GEN >= 5 +#elif GFX_VER >= 5 vb[idx].BufferAccessType = stride > 0 ? VERTEXDATA : INSTANCEDATA; vb[idx].EndAddress = vb[idx].BufferStartingAddress; vb[idx].EndAddress.offset += size - 1; -#elif GEN_GEN == 4 +#elif GFX_VER == 4 vb[idx].BufferAccessType = stride > 0 ? VERTEXDATA : INSTANCEDATA; vb[idx].MaxIndex = stride > 0 ? size / stride : 0; #endif @@ -482,22 +482,22 @@ blorp_emit_vertex_elements(struct blorp_batch *batch, * components using an element specifier. Instead one has separate * 3DSTATE_VF_SGVS (System Generated Value Setup) state packet for it. */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 .Component1Control = VFCOMP_STORE_0, -#elif GEN_GEN >= 5 +#elif GFX_VER >= 5 .Component1Control = VFCOMP_STORE_IID, #else .Component1Control = VFCOMP_STORE_0, #endif .Component2Control = VFCOMP_STORE_0, .Component3Control = VFCOMP_STORE_0, -#if GEN_GEN <= 5 +#if GFX_VER <= 5 .DestinationElementOffset = slot * 4, #endif }; slot++; -#if GEN_GEN <= 5 +#if GFX_VER <= 5 /* On Iron Lake and earlier, a native device coordinates version of the * position goes right after the normal VUE header and before position. * Since w == 1 for all of our coordinates, this is just a copy of the @@ -526,7 +526,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch, .Component1Control = VFCOMP_STORE_SRC, .Component2Control = VFCOMP_STORE_SRC, .Component3Control = VFCOMP_STORE_1_FP, -#if GEN_GEN <= 5 +#if GFX_VER <= 5 .DestinationElementOffset = slot * 4, #endif }; @@ -542,7 +542,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch, .Component1Control = VFCOMP_STORE_SRC, .Component2Control = VFCOMP_STORE_SRC, .Component3Control = VFCOMP_STORE_SRC, -#if GEN_GEN <= 5 +#if GFX_VER <= 5 .DestinationElementOffset = slot * 4, #endif }; @@ -564,7 +564,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch, vf.StatisticsEnable = false; } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* Overwrite Render Target Array Index (2nd dword) in the VUE header with * primitive instance identifier. This is used for layered clears. */ @@ -597,11 +597,11 @@ blorp_emit_cc_viewport(struct blorp_batch *batch) vp.MaximumDepth = 1.0; } -#if GEN_GEN >= 7 +#if GFX_VER >= 7 blorp_emit(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), vsp) { vsp.CCViewportPointer = cc_vp_offset; } -#elif GEN_GEN == 6 +#elif GFX_VER == 6 blorp_emit(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS), vsp) { vsp.CCViewportStateChange = true; vsp.PointertoCC_VIEWPORT = cc_vp_offset; @@ -631,16 +631,16 @@ blorp_emit_sampler_state(struct blorp_batch *batch) sampler.VAddressMagFilterRoundingEnable = true; sampler.UAddressMinFilterRoundingEnable = true; sampler.UAddressMagFilterRoundingEnable = true; -#if GEN_GEN > 6 +#if GFX_VER > 6 sampler.NonnormalizedCoordinateEnable = true; #endif } -#if GEN_GEN >= 7 +#if GFX_VER >= 7 blorp_emit(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_PS), ssp) { ssp.PointertoPSSamplerState = offset; } -#elif GEN_GEN == 6 +#elif GFX_VER == 6 blorp_emit(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS), ssp) { ssp.VSSamplerStateChange = true; ssp.GSSamplerStateChange = true; @@ -654,16 +654,16 @@ blorp_emit_sampler_state(struct blorp_batch *batch) /* What follows is the code for setting up a "pipeline" on Sandy Bridge and * later hardware. This file will be included by i965 for gen4-5 as well, so - * this code is guarded by GEN_GEN >= 6. + * this code is guarded by GFX_VER >= 6. */ -#if GEN_GEN >= 6 +#if GFX_VER >= 6 static void blorp_emit_vs_config(struct blorp_batch *batch, const struct blorp_params *params) { struct brw_vs_prog_data *vs_prog_data = params->vs_prog_data; - assert(!vs_prog_data || GEN_GEN < 11 || + assert(!vs_prog_data || GFX_VER < 11 || vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8); blorp_emit(batch, GENX(3DSTATE_VS), vs) { @@ -681,7 +681,7 @@ blorp_emit_vs_config(struct blorp_batch *batch, vs.MaximumNumberofThreads = batch->blorp->isl_dev->info->max_vs_threads - 1; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 vs.SIMD8DispatchEnable = vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8; #endif @@ -715,10 +715,10 @@ blorp_emit_sf_config(struct blorp_batch *batch, * (rendering rectangle (RECTLIST) objects. */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 blorp_emit(batch, GENX(3DSTATE_SF), sf) { -#if GEN_GEN >= 12 +#if GFX_VER >= 12 sf.DerefBlockSize = urb_deref_block_size; #endif } @@ -740,13 +740,13 @@ blorp_emit_sf_config(struct blorp_batch *batch, sbe.ForceVertexURBEntryReadLength = true; sbe.ForceVertexURBEntryReadOffset = true; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 for (unsigned i = 0; i < 32; i++) sbe.AttributeActiveComponentFormat[i] = ACF_XYZW; #endif } -#elif GEN_GEN >= 7 +#elif GFX_VER >= 7 blorp_emit(batch, GENX(3DSTATE_SF), sf) { sf.FrontFaceFillMode = FILL_MODE_SOLID; @@ -755,7 +755,7 @@ blorp_emit_sf_config(struct blorp_batch *batch, sf.MultisampleRasterizationMode = params->num_samples > 1 ? MSRASTMODE_ON_PATTERN : MSRASTMODE_OFF_PIXEL; -#if GEN_GEN == 7 +#if GFX_VER == 7 sf.DepthBufferSurfaceFormat = params->depth_format; #endif } @@ -772,7 +772,7 @@ blorp_emit_sf_config(struct blorp_batch *batch, } } -#else /* GEN_GEN <= 6 */ +#else /* GFX_VER <= 6 */ blorp_emit(batch, GENX(3DSTATE_SF), sf) { sf.FrontFaceFillMode = FILL_MODE_SOLID; @@ -792,7 +792,7 @@ blorp_emit_sf_config(struct blorp_batch *batch, } } -#endif /* GEN_GEN */ +#endif /* GFX_VER */ } static void @@ -810,7 +810,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, * configure the WM state whether or not there is a WM program. */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 blorp_emit(batch, GENX(3DSTATE_WM), wm); @@ -823,7 +823,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, } /* SAMPLER_STATE prefetching is broken on Gen11 - WA_1606682166 */ - if (GEN_GEN == 11) + if (GFX_VER == 11) ps.SamplerCount = 0; if (prog_data) { @@ -839,7 +839,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, * Since 16x MSAA is first introduced on SKL, we don't need to apply * the workaround on any older hardware. */ - if (GEN_GEN >= 9 && !prog_data->persample_dispatch && + if (GFX_VER >= 9 && !prog_data->persample_dispatch && params->num_samples == 16) { assert(ps._8PixelDispatchEnable || ps._16PixelDispatchEnable); ps._32PixelDispatchEnable = false; @@ -867,7 +867,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, * * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1. */ - if (GEN_GEN >= 9) + if (GFX_VER >= 9) ps.MaximumNumberofThreadsPerPSD = 64 - 1; else ps.MaximumNumberofThreadsPerPSD = 64 - 2; @@ -875,13 +875,13 @@ blorp_emit_ps_config(struct blorp_batch *batch, switch (params->fast_clear_op) { case ISL_AUX_OP_NONE: break; -#if GEN_GEN >= 10 +#if GFX_VER >= 10 case ISL_AUX_OP_AMBIGUATE: ps.RenderTargetFastClearEnable = true; ps.RenderTargetResolveType = FAST_CLEAR_0; break; #endif -#if GEN_GEN >= 9 +#if GFX_VER >= 9 case ISL_AUX_OP_PARTIAL_RESOLVE: ps.RenderTargetResolveType = RESOLVE_PARTIAL; break; @@ -907,7 +907,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, psx.AttributeEnable = prog_data->num_varying_inputs > 0; psx.PixelShaderIsPerSample = prog_data->persample_dispatch; psx.PixelShaderComputedDepthMode = prog_data->computed_depth_mode; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 psx.PixelShaderComputesStencil = prog_data->computed_stencil; #endif } @@ -916,7 +916,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, psx.PixelShaderKillsPixel = true; } -#elif GEN_GEN >= 7 +#elif GFX_VER >= 7 blorp_emit(batch, GENX(3DSTATE_WM), wm) { switch (params->hiz_op) { @@ -1006,7 +1006,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, } } -#else /* GEN_GEN <= 6 */ +#else /* GFX_VER <= 6 */ blorp_emit(batch, GENX(3DSTATE_WM), wm) { wm.MaximumNumberofThreads = @@ -1068,7 +1068,7 @@ blorp_emit_ps_config(struct blorp_batch *batch, } } -#endif /* GEN_GEN */ +#endif /* GFX_VER */ } static uint32_t @@ -1104,16 +1104,16 @@ blorp_emit_blend_state(struct blorp_batch *batch, blorp_flush_range(batch, state, size); -#if GEN_GEN >= 7 +#if GFX_VER >= 7 blorp_emit(batch, GENX(3DSTATE_BLEND_STATE_POINTERS), sp) { sp.BlendStatePointer = offset; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 sp.BlendStatePointerValid = true; #endif } #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 blorp_emit(batch, GENX(3DSTATE_PS_BLEND), ps_blend) { ps_blend.HasWriteableRT = true; } @@ -1128,15 +1128,15 @@ blorp_emit_color_calc_state(struct blorp_batch *batch, { uint32_t offset; blorp_emit_dynamic(batch, GENX(COLOR_CALC_STATE), cc, 64, &offset) { -#if GEN_GEN <= 8 +#if GFX_VER <= 8 cc.StencilReferenceValue = params->stencil_ref; #endif } -#if GEN_GEN >= 7 +#if GFX_VER >= 7 blorp_emit(batch, GENX(3DSTATE_CC_STATE_POINTERS), sp) { sp.ColorCalcStatePointer = offset; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 sp.ColorCalcStatePointerValid = true; #endif } @@ -1149,7 +1149,7 @@ static uint32_t blorp_emit_depth_stencil_state(struct blorp_batch *batch, const struct blorp_params *params) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 struct GENX(3DSTATE_WM_DEPTH_STENCIL) ds = { GENX(3DSTATE_WM_DEPTH_STENCIL_header), }; @@ -1190,12 +1190,12 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch, ds.StencilPassDepthPassOp = STENCILOP_REPLACE; ds.StencilWriteMask = params->stencil_mask; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 ds.StencilReferenceValue = params->stencil_ref; #endif } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 uint32_t offset = 0; uint32_t *dw = blorp_emit_dwords(batch, GENX(3DSTATE_WM_DEPTH_STENCIL_length)); @@ -1212,7 +1212,7 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch, blorp_flush_range(batch, state, GENX(DEPTH_STENCIL_STATE_length) * 4); #endif -#if GEN_GEN == 7 +#if GFX_VER == 7 blorp_emit(batch, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), sp) { sp.PointertoDEPTH_STENCIL_STATE = offset; } @@ -1228,14 +1228,14 @@ blorp_emit_3dstate_multisample(struct blorp_batch *batch, blorp_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms) { ms.NumberofMultisamples = __builtin_ffs(params->num_samples) - 1; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* The PRM says that this bit is valid only for DX9: * * SW can choose to set this bit only for DX9 API. DX10/OGL API's * should not have any effect by setting or not setting this bit. */ ms.PixelPositionOffsetEnable = false; -#elif GEN_GEN >= 7 +#elif GFX_VER >= 7 switch (params->num_samples) { case 1: @@ -1277,7 +1277,7 @@ blorp_emit_pipeline(struct blorp_batch *batch, color_calc_state_offset = blorp_emit_color_calc_state(batch, params); depth_stencil_state_offset = blorp_emit_depth_stencil_state(batch, params); -#if GEN_GEN == 6 +#if GFX_VER == 6 /* 3DSTATE_CC_STATE_POINTERS * * The pointer offsets are relative to @@ -1303,14 +1303,14 @@ blorp_emit_pipeline(struct blorp_batch *batch, (void)depth_stencil_state_offset; #endif -#if GEN_GEN >= 12 +#if GFX_VER >= 12 blorp_emit(batch, GENX(3DSTATE_CONSTANT_ALL), pc) { /* Update empty push constants for all stages (bitmask = 11111b) */ pc.ShaderUpdateEnable = 0x1f; } #else blorp_emit(batch, GENX(3DSTATE_CONSTANT_VS), vs); -#if GEN_GEN >= 7 +#if GFX_VER >= 7 blorp_emit(batch, GENX(3DSTATE_CONSTANT_HS), hs); blorp_emit(batch, GENX(3DSTATE_CONSTANT_DS), DS); #endif @@ -1338,7 +1338,7 @@ blorp_emit_pipeline(struct blorp_batch *batch, * We've already done one at the start of the BLORP operation. */ blorp_emit_vs_config(batch, params); -#if GEN_GEN >= 7 +#if GFX_VER >= 7 blorp_emit(batch, GENX(3DSTATE_HS), hs); blorp_emit(batch, GENX(3DSTATE_TE), te); blorp_emit(batch, GENX(3DSTATE_DS), DS); @@ -1355,7 +1355,7 @@ blorp_emit_pipeline(struct blorp_batch *batch, blorp_emit_cc_viewport(batch); -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* Disable Primitive Replication. */ blorp_emit(batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr); #endif @@ -1363,9 +1363,9 @@ blorp_emit_pipeline(struct blorp_batch *batch, /******** This is the end of the pipeline setup code ********/ -#endif /* GEN_GEN >= 6 */ +#endif /* GFX_VER >= 6 */ -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void blorp_emit_memcpy(struct blorp_batch *batch, struct blorp_address dst, @@ -1375,7 +1375,7 @@ blorp_emit_memcpy(struct blorp_batch *batch, assert(size % 4 == 0); for (unsigned dw = 0; dw < size; dw += 4) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 blorp_emit(batch, GENX(MI_COPY_MEM_MEM), cp) { cp.DestinationMemoryAddress = dst; cp.SourceMemoryAddress = src; @@ -1432,7 +1432,7 @@ blorp_emit_surface_state(struct blorp_batch *batch, (surface->aux_addr.buffer != NULL); isl_channel_mask_t write_disable_mask = 0; - if (is_render_target && GEN_GEN <= 5) { + if (is_render_target && GFX_VER <= 5) { if (color_write_disables[0]) write_disable_mask |= ISL_CHANNEL_RED_BIT; if (color_write_disables[1]) @@ -1444,7 +1444,7 @@ blorp_emit_surface_state(struct blorp_batch *batch, } const bool use_clear_address = - GEN_GEN >= 10 && (surface->clear_color_addr.buffer != NULL); + GFX_VER >= 10 && (surface->clear_color_addr.buffer != NULL); isl_surf_fill_state(batch->blorp->isl_dev, state, .surf = &surf, .view = &surface->view, @@ -1476,13 +1476,13 @@ blorp_emit_surface_state(struct blorp_batch *batch, } if (aux_usage != ISL_AUX_USAGE_NONE && surface->clear_color_addr.buffer) { -#if GEN_GEN >= 10 +#if GFX_VER >= 10 assert((surface->clear_color_addr.offset & 0x3f) == 0); uint32_t *clear_addr = state + isl_dev->ss.clear_color_state_offset; blorp_surface_reloc(batch, state_offset + isl_dev->ss.clear_color_state_offset, surface->clear_color_addr, *clear_addr); -#elif GEN_GEN >= 7 +#elif GFX_VER >= 7 /* Fast clears just whack the AUX surface and don't actually use the * clear color for anything. We can avoid the MI memcpy on that case. */ @@ -1514,15 +1514,15 @@ blorp_emit_null_surface_state(struct blorp_batch *batch, .MinimumArrayElement = surface->view.base_array_layer, .Depth = surface->view.array_len - 1, .RenderTargetViewExtent = surface->view.array_len - 1, -#if GEN_GEN >= 6 +#if GFX_VER >= 6 .NumberofMultisamples = ffs(surface->surf.samples) - 1, #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 .SurfaceArray = surface->surf.dim != ISL_SURF_DIM_3D, #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 .TileMode = YMAJOR, #else .TiledSurface = true, @@ -1578,7 +1578,7 @@ blorp_emit_surface_states(struct blorp_batch *batch, } } -#if GEN_GEN >= 7 +#if GFX_VER >= 7 if (has_indirect_clear_color) { /* Updating a surface state object may require that the state cache be * invalidated. From the SKL PRM, Shared Functions -> State -> State @@ -1591,14 +1591,14 @@ blorp_emit_surface_states(struct blorp_batch *batch, */ blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { pipe.StateCacheInvalidationEnable = true; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pipe.TileCacheFlushEnable = true; #endif } } #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), bt); blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_HS), bt); blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_DS), bt); @@ -1607,7 +1607,7 @@ blorp_emit_surface_states(struct blorp_batch *batch, blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS), bt) { bt.PointertoPSBindingTable = bind_offset; } -#elif GEN_GEN >= 6 +#elif GFX_VER >= 6 blorp_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS), bt) { bt.PSBindingTableChange = true; bt.PointertoPSBindingTable = bind_offset; @@ -1651,7 +1651,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch, info.hiz_surf = ¶ms->depth.aux_surf; struct blorp_address hiz_address = params->depth.aux_addr; -#if GEN_GEN == 6 +#if GFX_VER == 6 /* Sandy bridge hardware does not technically support mipmapped HiZ. * However, we have a special layout that allows us to make it work * anyway by manually offsetting to the specified miplevel. @@ -1677,7 +1677,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch, info.stencil_aux_usage = params->stencil.aux_usage; struct blorp_address stencil_address = params->stencil.addr; -#if GEN_GEN == 6 +#if GFX_VER == 6 /* Sandy bridge hardware does not technically support mipmapped stencil. * However, we have a special layout that allows us to make it work * anyway by manually offsetting to the specified miplevel. @@ -1697,7 +1697,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch, isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info); -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* GEN:BUG:1408224581 * * Workaround: Gen12LP Astep only An additional pipe control with @@ -1712,7 +1712,7 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch, #endif } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The * depth/stencil buffer extents are ignored to handle APIs which perform * clearing operations without such information. @@ -1831,7 +1831,7 @@ blorp_update_clear_color(UNUSED struct blorp_batch *batch, enum isl_aux_op op) { if (info->clear_color_addr.buffer && op == ISL_AUX_OP_FAST_CLEAR) { -#if GEN_GEN == 11 +#if GFX_VER == 11 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) { pipe.CommandStreamerStallEnable = true; } @@ -1870,7 +1870,7 @@ blorp_update_clear_color(UNUSED struct blorp_batch *batch, pipe.StateCacheInvalidationEnable = true; pipe.TextureCacheInvalidationEnable = true; } -#elif GEN_GEN >= 9 +#elif GFX_VER >= 9 /* According to GEN:BUG:2201730850, in the Clear Color Programming Note * under the Red channel, "Software shall write the converted Depth @@ -1880,7 +1880,7 @@ blorp_update_clear_color(UNUSED struct blorp_batch *batch, * and simply perform the conversion for all depth formats. */ union isl_color_value fixed_color = info->clear_color; - if (GEN_GEN == 12 && isl_surf_usage_is_depth(info->surf.usage)) { + if (GFX_VER == 12 && isl_surf_usage_is_depth(info->surf.usage)) { isl_color_value_pack(&info->clear_color, info->surf.format, fixed_color.u32); } @@ -1890,7 +1890,7 @@ blorp_update_clear_color(UNUSED struct blorp_batch *batch, sdi.Address = info->clear_color_addr; sdi.Address.offset += i * 4; sdi.ImmediateData = fixed_color.u32[i]; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 if (i == 3) sdi.ForceWriteCompletionCheck = true; #endif @@ -1905,7 +1905,7 @@ blorp_update_clear_color(UNUSED struct blorp_batch *batch, * surface format by software, will be stored. * */ -#if GEN_GEN >= 12 +#if GFX_VER >= 12 if (isl_surf_usage_is_depth(info->surf.usage)) { blorp_emit(batch, GENX(MI_STORE_DATA_IMM), sdi) { sdi.Address = info->clear_color_addr; @@ -1916,7 +1916,7 @@ blorp_update_clear_color(UNUSED struct blorp_batch *batch, } #endif -#elif GEN_GEN >= 7 +#elif GFX_VER >= 7 blorp_emit(batch, GENX(MI_STORE_DATA_IMM), sdi) { sdi.Address = info->clear_color_addr; sdi.ImmediateData = ISL_CHANNEL_SELECT_RED << 25 | @@ -1964,7 +1964,7 @@ blorp_exec(struct blorp_batch *batch, const struct blorp_params *params) blorp_update_clear_color(batch, ¶ms->depth, params->hiz_op); } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 if (params->hiz_op != ISL_AUX_OP_NONE) { blorp_emit_gen8_hiz_op(batch, params); return; @@ -1986,7 +1986,7 @@ blorp_exec(struct blorp_batch *batch, const struct blorp_params *params) blorp_emit(batch, GENX(3DPRIMITIVE), prim) { prim.VertexAccessType = SEQUENTIAL; prim.PrimitiveTopologyType = _3DPRIM_RECTLIST; -#if GEN_GEN >= 7 +#if GFX_VER >= 7 prim.PredicateEnable = batch->flags & BLORP_BATCH_PREDICATE_ENABLE; #endif prim.VertexCountPerInstance = 3; diff --git a/src/intel/common/intel_guardband.h b/src/intel/common/intel_guardband.h index e1a1fb53f0f..d8380a9839c 100644 --- a/src/intel/common/intel_guardband.h +++ b/src/intel/common/intel_guardband.h @@ -65,12 +65,12 @@ intel_calculate_guardband_size(uint32_t fb_width, uint32_t fb_height, * * So, limit the guardband to 16K on Gen7+ and 8K on Sandybridge. */ - const float gb_size = GEN_GEN >= 7 ? 16384.0f : 8192.0f; + const float gb_size = GFX_VER >= 7 ? 16384.0f : 8192.0f; /* Workaround: prevent gpu hangs on SandyBridge * by disabling guardband clipping for odd dimensions. */ - if (GEN_GEN == 6 && (fb_width & 1 || fb_height & 1)) { + if (GFX_VER == 6 && (fb_width & 1 || fb_height & 1)) { *xmin = -1.0f; *xmax = 1.0f; *ymin = -1.0f; diff --git a/src/intel/common/intel_sample_positions.h b/src/intel/common/intel_sample_positions.h index 0976afd340e..b8d09a5bdb1 100644 --- a/src/intel/common/intel_sample_positions.h +++ b/src/intel/common/intel_sample_positions.h @@ -55,12 +55,12 @@ intel_get_sample_positions(int samples) } /* Examples: - * in case of GEN_GEN < 8: + * in case of GFX_VER < 8: * INTEL_SAMPLE_POS_ELEM(ms.Sample, info->pSampleLocations, 0); expands to: * ms.Sample0XOffset = info->pSampleLocations[0].x; * ms.Sample0YOffset = info->pSampleLocations[0].y; * - * in case of GEN_GEN >= 8: + * in case of GFX_VER >= 8: * INTEL_SAMPLE_POS_ELEM(sp._16xSample, info->pSampleLocations, 0); expands to: * sp._16xSample0XOffset = info->pSampleLocations[0].x; * sp._16xSample0YOffset = info->pSampleLocations[0].y; diff --git a/src/intel/common/mi_builder.h b/src/intel/common/mi_builder.h index ca5b80c0372..25bcad83776 100644 --- a/src/intel/common/mi_builder.h +++ b/src/intel/common/mi_builder.h @@ -103,7 +103,7 @@ struct mi_value { struct mi_reg_num { uint32_t num; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 bool cs; #endif }; @@ -111,7 +111,7 @@ struct mi_reg_num { static inline struct mi_reg_num mi_adjust_reg_num(uint32_t reg) { -#if GEN_GEN >= 11 +#if GFX_VER >= 11 bool cs = reg >= 0x2000 && reg < 0x4000; return (struct mi_reg_num) { .num = reg - (cs ? 0x2000 : 0), @@ -122,7 +122,7 @@ mi_adjust_reg_num(uint32_t reg) #endif } -#if GEN_GEN >= 9 +#if GFX_VER >= 9 #define MI_BUILDER_MAX_MATH_DWORDS 256 #else #define MI_BUILDER_MAX_MATH_DWORDS 64 @@ -388,7 +388,7 @@ _mi_copy_no_unref(struct mi_builder *b, mi_builder_pack(b, GENX(MI_LOAD_REGISTER_IMM), dw, lri) { lri.DWordLength = GENX(MI_LOAD_REGISTER_IMM_length) + 2 - GENX(MI_LOAD_REGISTER_IMM_length_bias); -#if GEN_GEN >= 11 +#if GFX_VER >= 11 lri.AddCSMMIOStartOffset = reg.cs; #endif } @@ -397,7 +397,7 @@ _mi_copy_no_unref(struct mi_builder *b, dw[3] = reg.num + 4; dw[4] = src.imm >> 32; } else { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 assert(dst.type == MI_VALUE_TYPE_MEM64); uint32_t *dw = (uint32_t *)__gen_get_batch_dwords(b->user_data, GENX(MI_STORE_DATA_IMM_length) + 1); @@ -441,7 +441,7 @@ _mi_copy_no_unref(struct mi_builder *b, case MI_VALUE_TYPE_IMM: mi_builder_emit(b, GENX(MI_STORE_DATA_IMM), sdi) { sdi.Address = dst.addr; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 sdi.ForceWriteCompletionCheck = true; #endif sdi.ImmediateData = src.imm; @@ -450,7 +450,7 @@ _mi_copy_no_unref(struct mi_builder *b, case MI_VALUE_TYPE_MEM32: case MI_VALUE_TYPE_MEM64: -#if GEN_GEN >= 8 +#if GFX_VER >= 8 mi_builder_emit(b, GENX(MI_COPY_MEM_MEM), cmm) { cmm.DestinationMemoryAddress = dst.addr; cmm.SourceMemoryAddress = src.addr; @@ -472,7 +472,7 @@ _mi_copy_no_unref(struct mi_builder *b, mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { struct mi_reg_num reg = mi_adjust_reg_num(src.reg); srm.RegisterAddress = reg.num; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 srm.AddCSMMIOStartOffset = reg.cs; #endif srm.MemoryAddress = dst.addr; @@ -490,7 +490,7 @@ _mi_copy_no_unref(struct mi_builder *b, mi_builder_emit(b, GENX(MI_LOAD_REGISTER_IMM), lri) { struct mi_reg_num reg = mi_adjust_reg_num(dst.reg); lri.RegisterOffset = reg.num; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 lri.AddCSMMIOStartOffset = reg.cs; #endif lri.DataDWord = src.imm; @@ -502,7 +502,7 @@ _mi_copy_no_unref(struct mi_builder *b, mi_builder_emit(b, GENX(MI_LOAD_REGISTER_MEM), lrm) { struct mi_reg_num reg = mi_adjust_reg_num(dst.reg); lrm.RegisterAddress = reg.num; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 lrm.AddCSMMIOStartOffset = reg.cs; #endif lrm.MemoryAddress = src.addr; @@ -516,12 +516,12 @@ _mi_copy_no_unref(struct mi_builder *b, mi_builder_emit(b, GENX(MI_LOAD_REGISTER_REG), lrr) { struct mi_reg_num reg = mi_adjust_reg_num(src.reg); lrr.SourceRegisterAddress = reg.num; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 lrr.AddCSMMIOStartOffsetSource = reg.cs; #endif reg = mi_adjust_reg_num(dst.reg); lrr.DestinationRegisterAddress = reg.num; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 lrr.AddCSMMIOStartOffsetDestination = reg.cs; #endif } @@ -648,7 +648,7 @@ mi_store_if(struct mi_builder *b, struct mi_value dst, struct mi_value src) mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { struct mi_reg_num reg = mi_adjust_reg_num(src.reg); srm.RegisterAddress = reg.num; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 srm.AddCSMMIOStartOffset = reg.cs; #endif srm.MemoryAddress = dst.addr; @@ -657,7 +657,7 @@ mi_store_if(struct mi_builder *b, struct mi_value dst, struct mi_value src) mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { struct mi_reg_num reg = mi_adjust_reg_num(src.reg + 4); srm.RegisterAddress = reg.num; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 srm.AddCSMMIOStartOffset = reg.cs; #endif srm.MemoryAddress = __gen_address_offset(dst.addr, 4); @@ -667,7 +667,7 @@ mi_store_if(struct mi_builder *b, struct mi_value dst, struct mi_value src) mi_builder_emit(b, GENX(MI_STORE_REGISTER_MEM), srm) { struct mi_reg_num reg = mi_adjust_reg_num(src.reg); srm.RegisterAddress = reg.num; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 srm.AddCSMMIOStartOffset = reg.cs; #endif srm.MemoryAddress = dst.addr; diff --git a/src/intel/common/tests/mi_builder_test.cpp b/src/intel/common/tests/mi_builder_test.cpp index 84e3ac8b0b5..431ce625ee9 100644 --- a/src/intel/common/tests/mi_builder_test.cpp +++ b/src/intel/common/tests/mi_builder_test.cpp @@ -131,18 +131,18 @@ public: gen_device_info devinfo; uint32_t batch_bo_handle; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 uint64_t batch_bo_addr; #endif uint32_t batch_offset; void *batch_map; -#if GEN_GEN < 8 +#if GFX_VER < 8 std::vector relocs; #endif uint32_t data_bo_handle; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 uint64_t data_bo_addr; #endif void *data_map; @@ -194,7 +194,7 @@ mi_builder_test::SetUp() (void *)&getparam), 0) << strerror(errno); ASSERT_TRUE(gen_get_device_info_from_pci_id(device_id, &devinfo)); - if (devinfo.gen != GEN_GEN || devinfo.is_haswell != (GFX_VERx10 == 75)) { + if (devinfo.gen != GFX_VER || devinfo.is_haswell != (GFX_VERx10 == 75)) { close(fd); fd = -1; continue; @@ -212,7 +212,7 @@ mi_builder_test::SetUp() (void *)&ctx_create), 0) << strerror(errno); ctx_id = ctx_create.ctx_id; - if (GEN_GEN >= 8) { + if (GFX_VER >= 8) { /* On gen8+, we require softpin */ int has_softpin; drm_i915_getparam getparam = drm_i915_getparam(); @@ -229,7 +229,7 @@ mi_builder_test::SetUp() ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, (void *)&gem_create), 0) << strerror(errno); batch_bo_handle = gem_create.handle; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 batch_bo_addr = 0xffffffffdff70000ULL; #endif @@ -257,7 +257,7 @@ mi_builder_test::SetUp() ASSERT_EQ(drmIoctl(fd, DRM_IOCTL_I915_GEM_CREATE, (void *)&gem_create), 0) << strerror(errno); data_bo_handle = gem_create.handle; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 data_bo_addr = 0xffffffffefff0000ULL; #endif @@ -309,7 +309,7 @@ mi_builder_test::submit_batch() objects[0].handle = data_bo_handle; objects[0].relocation_count = 0; objects[0].relocs_ptr = 0; -#if GEN_GEN >= 8 /* On gen8+, we pin everything */ +#if GFX_VER >= 8 /* On gen8+, we pin everything */ objects[0].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE; @@ -320,7 +320,7 @@ mi_builder_test::submit_batch() #endif objects[1].handle = batch_bo_handle; -#if GEN_GEN >= 8 /* On gen8+, we don't use relocations */ +#if GFX_VER >= 8 /* On gen8+, we don't use relocations */ objects[1].relocation_count = 0; objects[1].relocs_ptr = 0; objects[1].flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | @@ -355,7 +355,7 @@ uint64_t __gen_combine_address(mi_builder_test *test, void *location, address addr, uint32_t delta) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 uint64_t addr_u64 = addr.gem_handle == test->data_bo_handle ? test->data_bo_addr : test->batch_bo_addr; return addr_u64 + addr.offset + delta; diff --git a/src/intel/dev/gen_device_info.h b/src/intel/dev/gen_device_info.h index 3fdeeb08da9..1df37e01f8f 100644 --- a/src/intel/dev/gen_device_info.h +++ b/src/intel/dev/gen_device_info.h @@ -284,10 +284,10 @@ struct gen_device_info /** @} */ }; -#ifdef GEN_GEN +#ifdef GFX_VER #define gen_device_info_is_9lp(devinfo) \ - (GEN_GEN == 9 && ((devinfo)->is_broxton || (devinfo)->is_geminilake)) + (GFX_VER == 9 && ((devinfo)->is_broxton || (devinfo)->is_geminilake)) #else diff --git a/src/intel/genxml/gen_macros.h b/src/intel/genxml/gen_macros.h index be6c0b4f804..b09d29946e0 100644 --- a/src/intel/genxml/gen_macros.h +++ b/src/intel/genxml/gen_macros.h @@ -56,7 +56,7 @@ # error "The GFX_VERx10 macro must be defined" #endif -#define GEN_GEN ((GFX_VERx10) / 10) +#define GFX_VER ((GFX_VERx10) / 10) /* Prefixing macros */ #if (GFX_VERx10 == 40) diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index 075842657a8..2aa62e3d179 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -40,7 +40,7 @@ __gen_combine_address(__attribute__((unused)) void *data, #include "isl_priv.h" static const uint32_t isl_to_gen_ds_surftype[] = { -#if GEN_GEN >= 9 +#if GFX_VER >= 9 /* From the SKL PRM, "3DSTATE_DEPTH_STENCIL::SurfaceType": * * "If depth/stencil is enabled with 1D render target, depth/stencil @@ -107,15 +107,15 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, } if (info->depth_surf) { -#if GEN_GEN >= 7 +#if GFX_VER >= 7 db.DepthWriteEnable = true; #endif db.SurfaceBaseAddress = info->depth_address; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 db.MOCS = info->mocs; #endif -#if GEN_GEN <= 6 +#if GFX_VER <= 6 db.TiledSurface = info->depth_surf->tiling != ISL_TILING_LINEAR; db.TileWalk = info->depth_surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR : TILEWALK_XMAJOR; @@ -123,18 +123,18 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #endif db.SurfacePitch = info->depth_surf->row_pitch_B - 1; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 db.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(info->depth_surf) >> 2; #endif -#if GEN_GEN >= 12 +#if GFX_VER >= 12 db.ControlSurfaceEnable = db.DepthBufferCompressionEnable = isl_aux_usage_has_ccs(info->hiz_usage); #endif } -#if GEN_GEN == 5 || GEN_GEN == 6 +#if GFX_VER == 5 || GFX_VER == 6 const bool separate_stencil = info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT; if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) { @@ -144,7 +144,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, } #endif -#if GEN_GEN >= 6 +#if GFX_VER >= 6 struct GENX(3DSTATE_STENCIL_BUFFER) sb = { GENX(3DSTATE_STENCIL_BUFFER_header), }; @@ -153,10 +153,10 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #endif if (info->stencil_surf) { -#if GEN_GEN >= 7 && GEN_GEN < 12 +#if GFX_VER >= 7 && GFX_VER < 12 db.StencilWriteEnable = true; #endif -#if GEN_GEN >= 12 +#if GFX_VER >= 12 sb.StencilWriteEnable = true; sb.SurfaceType = SURFTYPE_2D; sb.Width = info->stencil_surf->logical_level0_px.width - 1; @@ -173,16 +173,16 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, sb.StencilBufferEnable = true; #endif sb.SurfaceBaseAddress = info->stencil_address; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 sb.MOCS = info->mocs; #endif sb.SurfacePitch = info->stencil_surf->row_pitch_B - 1; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 sb.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(info->stencil_surf) >> 2; #endif } else { -#if GEN_GEN >= 12 +#if GFX_VER >= 12 sb.SurfaceType = SURFTYPE_NULL; /* The docs seem to indicate that if surf-type is null, then we may need @@ -196,7 +196,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #endif } -#if GEN_GEN >= 6 +#if GFX_VER >= 6 struct GENX(3DSTATE_HIER_DEPTH_BUFFER) hiz = { GENX(3DSTATE_HIER_DEPTH_BUFFER_header), }; @@ -207,13 +207,13 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, assert(info->hiz_usage == ISL_AUX_USAGE_NONE || isl_aux_usage_has_hiz(info->hiz_usage)); if (isl_aux_usage_has_hiz(info->hiz_usage)) { - assert(GEN_GEN >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ); + assert(GFX_VER >= 12 || info->hiz_usage == ISL_AUX_USAGE_HIZ); db.HierarchicalDepthBufferEnable = true; hiz.SurfaceBaseAddress = info->hiz_address; hiz.MOCS = info->mocs; hiz.SurfacePitch = info->hiz_surf->row_pitch_B - 1; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 hiz.HierarchicalDepthBufferWriteThruEnable = info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT; @@ -250,7 +250,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, assert(info->depth_surf->samples == 1); #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* From the SKL PRM Vol2a: * * The interpretation of this field is dependent on Surface Type @@ -269,7 +269,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, #endif clear.DepthClearValueValid = true; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 clear.DepthClearValue = info->depth_clear_value; #else switch (info->depth_surf->format) { @@ -290,21 +290,21 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, } #endif } -#endif /* GEN_GEN >= 6 */ +#endif /* GFX_VER >= 6 */ /* Pack everything into the batch */ uint32_t *dw = batch; GENX(3DSTATE_DEPTH_BUFFER_pack)(NULL, dw, &db); dw += GENX(3DSTATE_DEPTH_BUFFER_length); -#if GEN_GEN >= 6 +#if GFX_VER >= 6 GENX(3DSTATE_STENCIL_BUFFER_pack)(NULL, dw, &sb); dw += GENX(3DSTATE_STENCIL_BUFFER_length); GENX(3DSTATE_HIER_DEPTH_BUFFER_pack)(NULL, dw, &hiz); dw += GENX(3DSTATE_HIER_DEPTH_BUFFER_length); -#if GEN_GEN == 12 +#if GFX_VER == 12 /* GEN:BUG:14010455700 * * To avoid sporadic corruptions “Set 0x7010[9] when Depth Buffer Surface diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index eefa7fa1060..9521b311ff9 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -39,46 +39,46 @@ __gen_combine_address(__attribute__((unused)) void *data, #include "isl_priv.h" -#if GEN_GEN >= 8 +#if GFX_VER >= 8 static const uint8_t isl_to_gen_halign[] = { [4] = HALIGN4, [8] = HALIGN8, [16] = HALIGN16, }; -#elif GEN_GEN >= 7 +#elif GFX_VER >= 7 static const uint8_t isl_to_gen_halign[] = { [4] = HALIGN_4, [8] = HALIGN_8, }; #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 static const uint8_t isl_to_gen_valign[] = { [4] = VALIGN4, [8] = VALIGN8, [16] = VALIGN16, }; -#elif GEN_GEN >= 6 +#elif GFX_VER >= 6 static const uint8_t isl_to_gen_valign[] = { [2] = VALIGN_2, [4] = VALIGN_4, }; #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 static const uint8_t isl_to_gen_tiling[] = { [ISL_TILING_LINEAR] = LINEAR, [ISL_TILING_X] = XMAJOR, [ISL_TILING_Y0] = YMAJOR, [ISL_TILING_Yf] = YMAJOR, [ISL_TILING_Ys] = YMAJOR, -#if GEN_GEN <= 11 +#if GFX_VER <= 11 [ISL_TILING_W] = WMAJOR, #endif }; #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static const uint32_t isl_to_gen_multisample_layout[] = { [ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS, [ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL, @@ -86,7 +86,7 @@ static const uint32_t isl_to_gen_multisample_layout[] = { }; #endif -#if GEN_GEN >= 12 +#if GFX_VER >= 12 static const uint32_t isl_to_gen_aux_mode[] = { [ISL_AUX_USAGE_NONE] = AUX_NONE, [ISL_AUX_USAGE_MC] = AUX_NONE, @@ -97,7 +97,7 @@ static const uint32_t isl_to_gen_aux_mode[] = { [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE, [ISL_AUX_USAGE_STC_CCS] = AUX_CCS_E, }; -#elif GEN_GEN >= 9 +#elif GFX_VER >= 9 static const uint32_t isl_to_gen_aux_mode[] = { [ISL_AUX_USAGE_NONE] = AUX_NONE, [ISL_AUX_USAGE_HIZ] = AUX_HIZ, @@ -105,7 +105,7 @@ static const uint32_t isl_to_gen_aux_mode[] = { [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D, [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E, }; -#elif GEN_GEN >= 8 +#elif GFX_VER >= 8 static const uint32_t isl_to_gen_aux_mode[] = { [ISL_AUX_USAGE_NONE] = AUX_NONE, [ISL_AUX_USAGE_HIZ] = AUX_HIZ, @@ -148,7 +148,7 @@ get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage) UNUSED static struct isl_extent3d get_image_alignment(const struct isl_surf *surf) { - if (GEN_GEN >= 9) { + if (GFX_VER >= 9) { if (isl_tiling_is_std_y(surf->tiling) || surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) { /* The hardware ignores the alignment values. Anyway, the surface's @@ -177,7 +177,7 @@ get_image_alignment(const struct isl_surf *surf) } } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 static uint32_t get_qpitch(const struct isl_surf *surf) { @@ -185,7 +185,7 @@ get_qpitch(const struct isl_surf *surf) default: unreachable("Bad isl_surf_dim"); case ISL_DIM_LAYOUT_GEN4_2D: - if (GEN_GEN >= 9) { + if (GFX_VER >= 9) { if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) { /* This is rather annoying and completely undocumented. It * appears that the hardware has a bug (or undocumented feature) @@ -242,7 +242,7 @@ get_qpitch(const struct isl_surf *surf) return 0; } } -#endif /* GEN_GEN >= 8 */ +#endif /* GFX_VER >= 8 */ void isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, @@ -285,7 +285,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.SurfaceFormat = info->view->format; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* The BSpec description of this field says: * * "This bit field, when set, indicates if the resource is created as @@ -318,7 +318,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, info->aux_usage == ISL_AUX_USAGE_STC_CCS; #endif -#if GEN_GEN <= 5 +#if GFX_VER <= 5 s.ColorBufferComponentWriteDisables = info->write_disables; #else assert(info->write_disables == 0); @@ -347,7 +347,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, * affected heights, we increment the height by 1 for the rendering * surface. */ - if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && + if (GFX_VER == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && info->surf->samples > 1 && (info->surf->logical_level0_px.height % 4) == 1) s.Height++; @@ -434,11 +434,11 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, unreachable("bad SurfaceType"); } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */ s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D && info->view->array_len > 1; -#elif GEN_GEN >= 7 +#elif GFX_VER >= 7 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D; #endif @@ -460,7 +460,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.MIPCountLOD = MAX(info->view->levels, 1) - 1; } -#if GEN_GEN >= 9 +#if GFX_VER >= 9 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail * Start LOD" to 15 to prevent the hardware from trying to use them. */ @@ -468,10 +468,10 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.MipTailStartLOD = 15; #endif -#if GEN_GEN >= 6 +#if GFX_VER >= 6 const struct isl_extent3d image_align = get_image_alignment(info->surf); s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height]; -#if GEN_GEN >= 7 +#if GFX_VER >= 7 s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width]; #endif #endif @@ -483,15 +483,15 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.SurfacePitch = info->surf->row_pitch_B - 1; } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 s.SurfaceQPitch = get_qpitch(info->surf) >> 2; -#elif GEN_GEN == 7 +#elif GFX_VER == 7 s.SurfaceArraySpacing = info->surf->array_pitch_span == ISL_ARRAY_PITCH_SPAN_COMPACT; #endif -#if GEN_GEN >= 8 - assert(GEN_GEN < 12 || info->surf->tiling != ISL_TILING_W); +#if GFX_VER >= 8 + assert(GFX_VER < 12 || info->surf->tiling != ISL_TILING_W); s.TileMode = isl_to_gen_tiling[info->surf->tiling]; #else s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR, @@ -499,13 +499,13 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, TILEWALK_XMAJOR, #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 s.RenderCacheReadWriteMode = WriteOnlyCache; #else s.RenderCacheReadWriteMode = 0; #endif -#if GEN_GEN >= 11 +#if GFX_VER >= 11 /* We've seen dEQP failures when enabling this bit with UINT formats, * which particularly affects blorp_copy() operations. It shouldn't * have any effect on UINT textures anyway, so disable it for them. @@ -521,9 +521,9 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.CubeFaceEnablePositiveX = 1; s.CubeFaceEnableNegativeX = 1; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 s.NumberofMultisamples = ffs(info->surf->samples) - 1; -#if GEN_GEN >= 7 +#if GFX_VER >= 7 s.MultisampledSurfaceStorageFormat = isl_to_gen_multisample_layout[info->surf->msaa_layout]; #endif @@ -543,7 +543,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.SurfaceBaseAddress = info->address; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 s.MOCS = info->mocs; #endif @@ -560,7 +560,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, assert(info->surf->logical_level0_px.array_len == 1); assert(info->aux_usage == ISL_AUX_USAGE_NONE); - if (GEN_GEN >= 8) { + if (GFX_VER >= 8) { /* Broadwell added more rules. */ assert(info->surf->samples == 1); if (isl_format_get_layout(info->view->format)->bpb == 8) @@ -569,13 +569,13 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, assert(info->x_offset_sa % 8 == 0); } -#if GEN_GEN >= 7 +#if GFX_VER >= 7 s.SurfaceArray = false; #endif } const unsigned x_div = 4; - const unsigned y_div = GEN_GEN >= 8 ? 4 : 2; + const unsigned y_div = GFX_VER >= 8 ? 4 : 2; assert(info->x_offset_sa % x_div == 0); assert(info->y_offset_sa % y_div == 0); s.XOffset = info->x_offset_sa / x_div; @@ -585,10 +585,10 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, assert(info->y_offset_sa == 0); #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 if (info->aux_usage != ISL_AUX_USAGE_NONE) { /* Check valid aux usages per-gen */ - if (GEN_GEN >= 12) { + if (GFX_VER >= 12) { assert(info->aux_usage == ISL_AUX_USAGE_MCS || info->aux_usage == ISL_AUX_USAGE_CCS_E || info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E || @@ -596,16 +596,16 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT || info->aux_usage == ISL_AUX_USAGE_MCS_CCS || info->aux_usage == ISL_AUX_USAGE_STC_CCS); - } else if (GEN_GEN >= 9) { + } else if (GFX_VER >= 9) { assert(info->aux_usage == ISL_AUX_USAGE_HIZ || info->aux_usage == ISL_AUX_USAGE_MCS || info->aux_usage == ISL_AUX_USAGE_CCS_D || info->aux_usage == ISL_AUX_USAGE_CCS_E); - } else if (GEN_GEN >= 8) { + } else if (GFX_VER >= 8) { assert(info->aux_usage == ISL_AUX_USAGE_HIZ || info->aux_usage == ISL_AUX_USAGE_MCS || info->aux_usage == ISL_AUX_USAGE_CCS_D); - } else if (GEN_GEN >= 7) { + } else if (GFX_VER >= 7) { assert(info->aux_usage == ISL_AUX_USAGE_MCS || info->aux_usage == ISL_AUX_USAGE_CCS_D); } @@ -616,7 +616,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, * * On gen12 HDC supports compression. */ - if (GEN_GEN < 12) + if (GFX_VER < 12) assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT)); if (isl_surf_usage_is_depth(info->surf->usage)) @@ -665,10 +665,10 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, } } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 s.MemoryCompressionEnable = info->aux_usage == ISL_AUX_USAGE_MC; #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage]; #else s.MCSEnable = true; @@ -685,8 +685,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, * On all earlier hardware, an aux surface is required for all forms * of compression. */ - if ((GEN_GEN < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) || - (GEN_GEN >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) { + if ((GFX_VER < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) || + (GFX_VER >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) { assert(info->aux_surf != NULL); @@ -698,7 +698,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, s.AuxiliarySurfaceBaseAddress = info->aux_address; s.AuxiliarySurfacePitch = pitch_in_tiles - 1; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* Auxiliary surfaces in ISL have compressed formats but the hardware * doesn't expect our definition of the compression, it expects qpitch * in units of samples on the main surface. @@ -709,14 +709,14 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, } #endif -#if GEN_GEN >= 8 && GEN_GEN < 11 +#if GFX_VER >= 8 && GFX_VER < 11 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes): * * This bit must be set for the following surface types: BC2_UNORM * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM */ - if (GEN_GEN >= 9 || dev->info->is_cherryview) { + if (GFX_VER >= 9 || dev->info->is_cherryview) { switch (info->view->format) { case ISL_FORMAT_BC2_UNORM: case ISL_FORMAT_BC3_UNORM: @@ -733,7 +733,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE * must be set. */ - if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ) + if (GFX_VER >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ) s.SamplerL2BypassModeDisable = true; break; } @@ -742,7 +742,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, if (isl_aux_usage_has_fast_clears(info->aux_usage)) { if (info->use_clear_address) { -#if GEN_GEN >= 10 +#if GFX_VER >= 10 s.ClearValueAddressEnable = true; s.ClearValueAddress = info->clear_address; #else @@ -750,7 +750,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, #endif } -#if GEN_GEN == 11 +#if GFX_VER == 11 /* * From BXML > GT > Shared Functions > vol5c Shared Functions > * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable: @@ -770,16 +770,16 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, } #endif -#if GEN_GEN >= 12 +#if GFX_VER >= 12 assert(info->use_clear_address); -#elif GEN_GEN >= 9 +#elif GFX_VER >= 9 if (!info->use_clear_address) { s.RedClearColor = info->clear_color.u32[0]; s.GreenClearColor = info->clear_color.u32[1]; s.BlueClearColor = info->clear_color.u32[2]; s.AlphaClearColor = info->clear_color.u32[3]; } -#elif GEN_GEN >= 7 +#elif GFX_VER >= 7 /* Prior to Sky Lake, we only have one bit for the clear color which * gives us 0 or 1 in whatever the surface's format happens to be. */ @@ -834,7 +834,7 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state, uint32_t num_elements = buffer_size / info->stride_B; - if (GEN_GEN >= 7) { + if (GFX_VER >= 7) { /* From the IVB PRM, SURFACE_STATE::Height, * * For typed buffer and structured buffer surfaces, the number @@ -857,15 +857,15 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state, s.SurfaceType = SURFTYPE_BUFFER; s.SurfaceFormat = info->format; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 s.SurfaceVerticalAlignment = isl_to_gen_valign[4]; -#if GEN_GEN >= 7 +#if GFX_VER >= 7 s.SurfaceHorizontalAlignment = isl_to_gen_halign[4]; s.SurfaceArray = false; #endif #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 s.Height = ((num_elements - 1) >> 7) & 0x3fff; s.Width = (num_elements - 1) & 0x7f; s.Depth = ((num_elements - 1) >> 21) & 0x3ff; @@ -875,7 +875,7 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state, s.Depth = ((num_elements - 1) >> 20) & 0x7f; #endif - if (GEN_GEN == 12 && dev->info->revision == 0) { + if (GFX_VER == 12 && dev->info->revision == 0) { /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer * textures with very close base addresses (delta < 64B) to corrupt each * other. We can sort-of work around this by making small buffer @@ -896,24 +896,24 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state, s.SurfacePitch = info->stride_B - 1; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 s.NumberofMultisamples = MULTISAMPLECOUNT_1; #endif -#if (GEN_GEN >= 8) +#if (GFX_VER >= 8) s.TileMode = LINEAR; #else s.TiledSurface = false; #endif -#if (GEN_GEN >= 8) +#if (GFX_VER >= 8) s.RenderCacheReadWriteMode = WriteOnlyCache; #else s.RenderCacheReadWriteMode = 0; #endif s.SurfaceBaseAddress = info->address; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 s.MOCS = info->mocs; #endif @@ -938,16 +938,16 @@ isl_genX(null_fill_state)(void *state, struct isl_extent3d size) * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1872 */ .SurfaceFormat = ISL_FORMAT_R32_UINT, -#if GEN_GEN >= 7 +#if GFX_VER >= 7 .SurfaceArray = size.depth > 1, #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 .TileMode = YMAJOR, #else .TiledSurface = true, .TileWalk = TILEWALK_YMAJOR, #endif -#if GEN_GEN == 7 +#if GFX_VER == 7 /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared * Functions" * @@ -964,7 +964,7 @@ isl_genX(null_fill_state)(void *state, struct isl_extent3d size) .Height = size.height - 1, .Depth = size.depth - 1, .RenderTargetViewExtent = size.depth - 1, -#if GEN_GEN <= 5 +#if GFX_VER <= 5 .ColorBufferComponentWriteDisables = 0xf, #endif }; diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c index b69fbedc398..a1ade7d2bde 100644 --- a/src/intel/vulkan/gen8_cmd_buffer.c +++ b/src/intel/vulkan/gen8_cmd_buffer.c @@ -33,7 +33,7 @@ #include "genxml/genX_pack.h" #include "common/intel_guardband.h" -#if GEN_GEN == 8 +#if GFX_VER == 8 void gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer) { @@ -148,7 +148,7 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) pc.DepthCacheFlushEnable = true; pc.CommandStreamerStallEnable = true; pc.RenderTargetCacheFlushEnable = true; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pc.TileCacheFlushEnable = true; /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must @@ -158,7 +158,7 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) #endif } -#if GEN_GEN == 9 +#if GFX_VER == 9 uint32_t cache_mode; anv_pack_struct(&cache_mode, GENX(CACHE_MODE_0), @@ -169,7 +169,7 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) lri.DataDWord = cache_mode; } -#elif GEN_GEN == 8 +#elif GFX_VER == 8 uint32_t cache_mode; anv_pack_struct(&cache_mode, GENX(CACHE_MODE_1), @@ -182,7 +182,7 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) lri.DataDWord = cache_mode; } -#endif /* GEN_GEN == 8 */ +#endif /* GFX_VER == 8 */ /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache * Flush bits is often necessary. We do it regardless because it's easier. @@ -195,7 +195,7 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) pc.DepthStallEnable = true; pc.DepthCacheFlushEnable = true; pc.RenderTargetCacheFlushEnable = true; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pc.TileCacheFlushEnable = true; #endif } @@ -204,7 +204,7 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) UNUSED static bool want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer) { - assert(GEN_GEN == 8); + assert(GFX_VER == 8); /* From the Broadwell PRM Vol. 2c CACHE_MODE_1::NP_PMA_FIX_ENABLE: * @@ -293,9 +293,9 @@ want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer) UNUSED static bool want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer) { - if (GEN_GEN > 9) + if (GFX_VER > 9) return false; - assert(GEN_GEN == 9); + assert(GFX_VER == 9); /* From the Skylake PRM Vol. 2c CACHE_MODE_1::STC PMA Optimization Enable: * @@ -426,7 +426,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) struct GENX(3DSTATE_SF) sf = { GENX(3DSTATE_SF_header), }; -#if GEN_GEN == 8 +#if GFX_VER == 8 if (cmd_buffer->device->info.is_cherryview) { sf.CHVLineWidth = d->line_width; } else { @@ -462,7 +462,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) * across different state packets for gen8 and gen9. We handle that by * using a big old #if switch here. */ -#if GEN_GEN == 8 +#if GFX_VER == 8 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS | ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) { struct anv_state cc_state = @@ -602,7 +602,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer) } #endif -#if GEN_GEN >= 12 +#if GFX_VER >= 12 if(cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE | ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS | ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE)) { diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index 4f1fabd0071..ea0abb128fb 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -87,7 +87,7 @@ blorp_get_surface_address(struct blorp_batch *blorp_batch, return 0ull; } -#if GEN_GEN >= 7 && GEN_GEN < 10 +#if GFX_VER >= 7 && GFX_VER < 10 static struct blorp_address blorp_get_surface_base_address(struct blorp_batch *batch) { @@ -229,7 +229,7 @@ genX(blorp_exec)(struct blorp_batch *batch, genX(cmd_buffer_emit_hashing_mode)(cmd_buffer, params->x1 - params->x0, params->y1 - params->y0, scale); -#if GEN_GEN >= 11 +#if GFX_VER >= 11 /* The PIPE_CONTROL command description says: * * "Whenever a Binding Table Index (BTI) used by a Render Taget Message @@ -243,7 +243,7 @@ genX(blorp_exec)(struct blorp_batch *batch, ANV_PIPE_STALL_AT_SCOREBOARD_BIT; #endif -#if GEN_GEN == 7 +#if GFX_VER == 7 /* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement * indirect fast-clear colors can cause GPU hangs if we don't stall first. * See genX(cmd_buffer_mi_memcpy) for more details. @@ -266,7 +266,7 @@ genX(blorp_exec)(struct blorp_batch *batch, blorp_exec(batch, params); -#if GEN_GEN >= 11 +#if GFX_VER >= 11 /* The PIPE_CONTROL command description says: * * "Whenever a Binding Table Index (BTI) used by a Render Taget Message diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index f9c4ad1bab3..1f630ac7826 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -71,10 +71,10 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) pc.DCFlushEnable = true; pc.RenderTargetCacheFlushEnable = true; pc.CommandStreamerStallEnable = true; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pc.TileCacheFlushEnable = true; #endif -#if GEN_GEN == 12 +#if GFX_VER == 12 /* GEN:BUG:1606662791: * * Software must program PIPE_CONTROL command with "HDC Pipeline @@ -87,7 +87,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) #endif } -#if GEN_GEN == 12 +#if GFX_VER == 12 /* GEN:BUG:1607854226: * * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline @@ -123,7 +123,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) sba.InstructionMOCS = mocs; sba.InstructionBaseAddressModifyEnable = true; -# if (GEN_GEN >= 8) +# if (GFX_VER >= 8) /* Broadwell requires that we specify a buffer size for a bunch of * these fields. However, since we will be growing the BO's live, we * just set them all to the maximum. @@ -162,7 +162,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) (struct anv_address) { .bo = NULL, .offset = 0xfffff000 }; sba.InstructionAccessUpperBoundModifyEnable = true; # endif -# if (GEN_GEN >= 9) +# if (GFX_VER >= 9) if (cmd_buffer->device->physical->use_softpin) { sba.BindlessSurfaceStateBaseAddress = (struct anv_address) { .bo = device->surface_state_pool.block_pool.bo, @@ -176,7 +176,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) sba.BindlessSurfaceStateMOCS = mocs; sba.BindlessSurfaceStateBaseAddressModifyEnable = true; # endif -# if (GEN_GEN >= 10) +# if (GFX_VER >= 10) sba.BindlessSamplerStateBaseAddress = (struct anv_address) { NULL, 0 }; sba.BindlessSamplerStateMOCS = mocs; sba.BindlessSamplerStateBaseAddressModifyEnable = true; @@ -184,7 +184,7 @@ genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) # endif } -#if GEN_GEN == 12 +#if GFX_VER == 12 /* GEN:BUG:1607854226: * * Put the pipeline back into its current mode. @@ -348,7 +348,7 @@ anv_can_fast_clear_color_view(struct anv_device * device, return false; /* On Broadwell and earlier, we can only handle 0/1 clear colors */ - if (GEN_GEN <= 8 && + if (GFX_VER <= 8 && !isl_color_value_is_zero_one(clear_color, iview->planes[0].isl.format)) return false; @@ -400,7 +400,7 @@ anv_can_hiz_clear_ds_view(struct anv_device *device, VkRect2D render_area) { /* We don't do any HiZ or depth fast-clears on gen7 yet */ - if (GEN_GEN == 7) + if (GFX_VER == 7) return false; /* If we're just clearing stencil, we can always HiZ clear */ @@ -436,7 +436,7 @@ anv_can_hiz_clear_ds_view(struct anv_device *device, * portion of a HiZ buffer. Testing has revealed that Gen8 only supports * returning 0.0f. Gens prior to gen8 do not support this feature at all. */ - if (GEN_GEN == 8 && anv_can_sample_with_hiz(&device->info, iview->image)) + if (GFX_VER == 8 && anv_can_sample_with_hiz(&device->info, iview->image)) return false; /* If we got here, then we can fast clear */ @@ -445,7 +445,7 @@ anv_can_hiz_clear_ds_view(struct anv_device *device, #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x)) -#if GEN_GEN == 12 +#if GFX_VER == 12 static void anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer, const struct anv_image *image, @@ -540,7 +540,7 @@ anv_image_init_aux_tt(struct anv_cmd_buffer *cmd_buffer, cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT; } -#endif /* GEN_GEN == 12 */ +#endif /* GFX_VER == 12 */ /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless * the initial layout is undefined, the HiZ buffer and depth buffer will @@ -559,7 +559,7 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer, if (image->planes[depth_plane].aux_usage == ISL_AUX_USAGE_NONE) return; -#if GEN_GEN == 12 +#if GFX_VER == 12 if ((initial_layout == VK_IMAGE_LAYOUT_UNDEFINED || initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) && cmd_buffer->device->physical->has_implicit_ccs && @@ -633,7 +633,7 @@ transition_stencil_buffer(struct anv_cmd_buffer *cmd_buffer, VkImageLayout final_layout, bool will_full_fast_clear) { -#if GEN_GEN == 7 +#if GFX_VER == 7 uint32_t plane = anv_image_aspect_to_plane(image->aspects, VK_IMAGE_ASPECT_STENCIL_BIT); @@ -661,7 +661,7 @@ transition_stencil_buffer(struct anv_cmd_buffer *cmd_buffer, base_level, level_count, base_layer, layer_count); } -#elif GEN_GEN == 12 +#elif GFX_VER == 12 uint32_t plane = anv_image_aspect_to_plane(image->aspects, VK_IMAGE_ASPECT_STENCIL_BIT); if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE) @@ -842,7 +842,7 @@ anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer, } #endif /* GFX_VERx10 >= 75 */ -#if GEN_GEN <= 8 +#if GFX_VER <= 8 static void anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer *cmd_buffer, const struct anv_image *image, @@ -883,7 +883,7 @@ anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer *cmd_buffer, mip.CompareOperation = COMPARE_SRCS_EQUAL; } } -#endif /* GEN_GEN <= 8 */ +#endif /* GFX_VER <= 8 */ static void anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer *cmd_buffer, @@ -897,11 +897,11 @@ anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer *cmd_buffer, { const uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect); -#if GEN_GEN >= 9 +#if GFX_VER >= 9 anv_cmd_compute_resolve_predicate(cmd_buffer, image, aspect, level, array_layer, resolve_op, fast_clear_supported); -#else /* GEN_GEN <= 8 */ +#else /* GFX_VER <= 8 */ anv_cmd_simple_resolve_predicate(cmd_buffer, image, aspect, level, array_layer, resolve_op, fast_clear_supported); @@ -985,9 +985,9 @@ init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer, struct anv_address addr = anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect); - if (GEN_GEN >= 9) { + if (GFX_VER >= 9) { const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev; - const unsigned num_dwords = GEN_GEN >= 10 ? + const unsigned num_dwords = GFX_VER >= 10 ? isl_dev->ss.clear_color_state_size / 4 : isl_dev->ss.clear_value_size / 4; for (unsigned i = 0; i < num_dwords; i++) { @@ -1009,7 +1009,7 @@ init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer, ISL_CHANNEL_SELECT_GREEN << 22 | ISL_CHANNEL_SELECT_BLUE << 19 | ISL_CHANNEL_SELECT_ALPHA << 16; - } else if (GEN_GEN == 7) { + } else if (GFX_VER == 7) { /* On IVB, the dword containing the clear values also contains * other fields that must be zero or can be zero. */ @@ -1041,7 +1041,7 @@ genX(copy_fast_clear_dwords)(struct anv_cmd_buffer *cmd_buffer, anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect); unsigned copy_size = cmd_buffer->device->isl_dev.ss.clear_value_size; -#if GEN_GEN == 7 +#if GFX_VER == 7 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is * in-flight when they are issued even if the memory touched is not @@ -1158,7 +1158,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer, if (initial_layout == VK_IMAGE_LAYOUT_UNDEFINED || initial_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) { -#if GEN_GEN == 12 +#if GFX_VER == 12 if (device->physical->has_implicit_ccs && devinfo->has_aux_map) { anv_image_init_aux_tt(cmd_buffer, image, aspect, base_level, level_count, @@ -1851,7 +1851,7 @@ genX(CmdExecuteCommands)( /* The secondary isn't counted in our VF cache tracking so we need to * invalidate the whole thing. */ - if (GEN_GEN >= 8 && GEN_GEN <= 9) { + if (GFX_VER >= 8 && GFX_VER <= 9) { primary->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_VF_CACHE_INVALIDATE_BIT; } @@ -1883,11 +1883,11 @@ void genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, const struct intel_l3_config *cfg) { - assert(cfg || GEN_GEN >= 12); + assert(cfg || GFX_VER >= 12); if (cfg == cmd_buffer->state.current_l3_config) return; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 /* On Gen11+ we use only one config, so verify it remains the same and skip * the stalling programming entirely. */ @@ -1940,7 +1940,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, } genX(emit_l3_config)(&cmd_buffer->batch, cmd_buffer->device, cfg); -#endif /* GEN_GEN >= 11 */ +#endif /* GFX_VER >= 11 */ cmd_buffer->state.current_l3_config = cfg; } @@ -1992,7 +1992,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) * add extra flushes in the case it knows that the engine is already * IDLE." */ - if (GEN_GEN == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)) + if (GFX_VER == 12 && (bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)) bits |= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT; /* If we're going to do an invalidate and we have a pending end-of-pipe @@ -2004,7 +2004,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT; } - if (GEN_GEN >= 12 && + if (GFX_VER >= 12 && ((bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT) || (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT))) { /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush @@ -2025,10 +2025,10 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which * invalidates the instruction cache */ - if (GEN_GEN == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)) + if (GFX_VER == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT)) bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT; - if ((GEN_GEN >= 8 && GEN_GEN <= 9) && + if ((GFX_VER >= 8 && GFX_VER <= 9) && (bits & ANV_PIPE_CS_STALL_BIT) && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) { /* If we are doing a VF cache invalidate AND a CS stall (it must be @@ -2052,7 +2052,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) * On Gen12 this is GEN:BUG:1607156449. */ if (bits & ANV_PIPE_POST_SYNC_BIT) { - if ((GEN_GEN == 9 || (GEN_GEN == 12 && devinfo->revision == 0 /* A0 */)) && + if ((GFX_VER == 9 || (GFX_VER == 12 && devinfo->revision == 0 /* A0 */)) && cmd_buffer->state.current_pipeline == GPGPU) bits |= ANV_PIPE_CS_STALL_BIT; bits &= ~ANV_PIPE_POST_SYNC_BIT; @@ -2061,7 +2061,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) if (bits & (ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT)) { anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) { -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pipe.TileCacheFlushEnable = bits & ANV_PIPE_TILE_CACHE_FLUSH_BIT; #endif pipe.DepthCacheFlushEnable = bits & ANV_PIPE_DEPTH_CACHE_FLUSH_BIT; @@ -2072,7 +2072,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must * be set with any PIPE_CONTROL with Depth Flush Enable bit set. */ -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pipe.DepthStallEnable = pipe.DepthCacheFlushEnable || (bits & ANV_PIPE_DEPTH_STALL_BIT); #else @@ -2199,7 +2199,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) * * This appears to hang Broadwell, so we restrict it to just gen9. */ - if (GEN_GEN == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) + if (GFX_VER == 9 && (bits & ANV_PIPE_VF_CACHE_INVALIDATE_BIT)) anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe); anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) { @@ -2220,13 +2220,13 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) * enabled to “Write Immediate Data” or “Write PS Depth Count” or * “Write Timestamp”. */ - if (GEN_GEN == 9 && pipe.VFCacheInvalidationEnable) { + if (GFX_VER == 9 && pipe.VFCacheInvalidationEnable) { pipe.PostSyncOperation = WriteImmediateData; pipe.Address = cmd_buffer->device->workaround_address; } } -#if GEN_GEN == 12 +#if GFX_VER == 12 if ((bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) && cmd_buffer->device->info.has_aux_map) { anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { @@ -2343,7 +2343,7 @@ cmd_buffer_alloc_push_constants(struct anv_cmd_buffer *cmd_buffer) if (stages == cmd_buffer->state.gfx.push_constant_stages) return; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 const unsigned push_constant_kb = 32; #elif GFX_VERx10 == 75 const unsigned push_constant_kb = cmd_buffer->device->info.gt == 3 ? 32 : 16; @@ -3035,7 +3035,7 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer, const struct anv_pipeline_bind_map *bind_map = &pipeline->shaders[stage]->bind_map; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 /* This field exists since Gen8. However, the Broadwell PRM says: * * "Constant Buffer Object Control State must be always programmed @@ -3104,7 +3104,7 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer, } } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 static void cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer *cmd_buffer, uint32_t shader_mask, @@ -3169,7 +3169,7 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer, struct anv_cmd_graphics_state *gfx_state = &cmd_buffer->state.gfx; const struct anv_graphics_pipeline *pipeline = gfx_state->pipeline; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 uint32_t nobuffer_stages = 0; #endif @@ -3249,7 +3249,7 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer, assert(bind_map->push_ranges[i].length == 0); } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* If this stage doesn't have any push constants, emit it later in a * single CONSTANT_ALL packet. */ @@ -3272,7 +3272,7 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer, cmd_buffer_emit_push_constant(cmd_buffer, stage, buffers, buffer_count); } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 if (nobuffer_stages) cmd_buffer_emit_push_constant_all(cmd_buffer, nobuffer_stages, NULL, 0); #endif @@ -3284,7 +3284,7 @@ static void cmd_buffer_emit_clip(struct anv_cmd_buffer *cmd_buffer) { const uint32_t clip_states = -#if GEN_GEN <= 7 +#if GFX_VER <= 7 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE | ANV_CMD_DIRTY_DYNAMIC_CULL_MODE | #endif @@ -3294,12 +3294,12 @@ cmd_buffer_emit_clip(struct anv_cmd_buffer *cmd_buffer) if ((cmd_buffer->state.gfx.dirty & clip_states) == 0) return; -#if GEN_GEN <= 7 +#if GFX_VER <= 7 const struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic; #endif struct GENX(3DSTATE_CLIP) clip = { GENX(3DSTATE_CLIP_header), -#if GEN_GEN <= 7 +#if GFX_VER <= 7 .FrontWinding = genX(vk_to_gen_front_face)[d->front_face], .CullMode = genX(vk_to_gen_cullmode)[d->cull_mode], #endif @@ -3379,7 +3379,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) .MOCS = anv_mocs(cmd_buffer->device, buffer->address.bo, ISL_SURF_USAGE_VERTEX_BUFFER_BIT), -#if GEN_GEN <= 7 +#if GFX_VER <= 7 .BufferAccessType = pipeline->vb[vb].instanced ? INSTANCEDATA : VERTEXDATA, .InstanceDataStepRate = pipeline->vb[vb].instance_divisor, #endif @@ -3388,7 +3388,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) .BufferStartingAddress = anv_address_add(buffer->address, offset), .NullVertexBuffer = offset >= buffer->size, -#if GEN_GEN >= 8 +#if GFX_VER >= 8 .BufferSize = size, #else /* XXX: to handle dynamic offset for older gens we might want @@ -3406,7 +3406,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) }; } -#if GEN_GEN >= 8 && GEN_GEN <= 9 +#if GFX_VER >= 8 && GFX_VER <= 9 genX(cmd_buffer_set_binding_for_gen8_vb_flush)(cmd_buffer, vb, state.BufferStartingAddress, state.BufferSize); @@ -3426,7 +3426,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) return; if ((cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_XFB_ENABLE) || - (GEN_GEN == 7 && (cmd_buffer->state.gfx.dirty & + (GFX_VER == 7 && (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE))) { /* We don't need any per-buffer dirty tracking because you're not * allowed to bind different XFB buffers while XFB is enabled. @@ -3434,7 +3434,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) for (unsigned idx = 0; idx < MAX_XFB_BUFFERS; idx++) { struct anv_xfb_binding *xfb = &cmd_buffer->state.xfb_bindings[idx]; anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) { -#if GEN_GEN < 12 +#if GFX_VER < 12 sob.SOBufferIndex = idx; #else sob._3DCommandOpcode = 0; @@ -3445,7 +3445,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) sob.MOCS = anv_mocs(cmd_buffer->device, xfb->buffer->address.bo, 0); sob.SurfaceBaseAddress = anv_address_add(xfb->buffer->address, xfb->offset); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 sob.SOBufferEnable = true; sob.StreamOffsetWriteEnable = false; /* Size is in DWords - 1 */ @@ -3464,7 +3464,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) } /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */ - if (GEN_GEN >= 10) + if (GFX_VER >= 10) cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT; } @@ -3480,7 +3480,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_PIPELINE) cmd_buffer->state.gfx.primitive_topology = pipeline->topology; -#if GEN_GEN <= 7 +#if GFX_VER <= 7 if (cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_VERTEX_BIT || cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_VERTEX_BIT) { /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1: @@ -3568,7 +3568,7 @@ emit_vertex_bo(struct anv_cmd_buffer *cmd_buffer, .MOCS = addr.bo ? anv_mocs(cmd_buffer->device, addr.bo, ISL_SURF_USAGE_VERTEX_BUFFER_BIT) : 0, .NullVertexBuffer = size == 0, -#if (GEN_GEN >= 8) +#if (GFX_VER >= 8) .BufferStartingAddress = addr, .BufferSize = size #else @@ -4043,7 +4043,7 @@ emit_draw_count_predicate_with_conditional_render( struct mi_value pred = mi_ult(b, mi_imm(draw_index), max); pred = mi_iand(b, pred, mi_reg64(ANV_PREDICATE_RESULT_REG)); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 mi_store(b, mi_reg32(MI_PREDICATE_RESULT), pred); #else /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser @@ -4398,7 +4398,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer) genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); } -#if GEN_GEN == 7 +#if GFX_VER == 7 static VkResult verify_cmd_parser(const struct anv_device *device, @@ -4483,7 +4483,7 @@ emit_compute_walker(struct anv_cmd_buffer *cmd_buffer, .BindingTablePointer = cmd_buffer->state.binding_tables[MESA_SHADER_COMPUTE].offset, .NumberofThreadsinGPGPUThreadGroup = cs_params.threads, - .SharedLocalMemorySize = encode_slm_size(GEN_GEN, + .SharedLocalMemorySize = encode_slm_size(GFX_VER, prog_data->base.total_shared), .BarrierEnable = prog_data->uses_barrier, }; @@ -4499,7 +4499,7 @@ emit_gpgpu_walker(struct anv_cmd_buffer *cmd_buffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) { - bool predicate = (GEN_GEN <= 7 && indirect) || + bool predicate = (GFX_VER <= 7 && indirect) || cmd_buffer->state.conditional_render_enabled; const struct anv_cs_parameters cs_params = anv_cs_parameters(pipeline); @@ -4607,7 +4607,7 @@ void genX(CmdDispatchIndirect)( anv_cmd_buffer_push_base_group_id(cmd_buffer, 0, 0, 0); -#if GEN_GEN == 7 +#if GFX_VER == 7 /* Linux 4.4 added command parser version 5 which allows the GPGPU * indirect dispatch registers to be written. */ @@ -4641,7 +4641,7 @@ void genX(CmdDispatchIndirect)( mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMY), size_y); mi_store(&b, mi_reg32(GPGPU_DISPATCHDIMZ), size_z); -#if GEN_GEN <= 7 +#if GFX_VER <= 7 /* predicate = (compute_dispatch_indirect_x_size == 0); */ mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), size_x); mi_store(&b, mi_reg64(MI_PREDICATE_SRC1), mi_imm(0)); @@ -4687,7 +4687,7 @@ void genX(CmdDispatchIndirect)( } #endif -#else /* GEN_GEN > 7 */ +#else /* GFX_VER > 7 */ if (cmd_buffer->state.conditional_render_enabled) genX(cmd_emit_conditional_render_predicate)(cmd_buffer); #endif @@ -4704,7 +4704,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, if (cmd_buffer->state.current_pipeline == pipeline) return; -#if GEN_GEN >= 8 && GEN_GEN < 10 +#if GFX_VER >= 8 && GFX_VER < 10 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT: * * Software must clear the COLOR_CALC_STATE Valid field in @@ -4718,7 +4718,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), t); #endif -#if GEN_GEN == 9 +#if GFX_VER == 9 if (pipeline == _3D) { /* There is a mid-object preemption workaround which requires you to * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However, @@ -4760,7 +4760,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, pc.DCFlushEnable = true; pc.PostSyncOperation = NoWrite; pc.CommandStreamerStallEnable = true; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pc.TileCacheFlushEnable = true; /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be @@ -4776,20 +4776,20 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer, pc.StateCacheInvalidationEnable = true; pc.InstructionCacheInvalidateEnable = true; pc.PostSyncOperation = NoWrite; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pc.TileCacheFlushEnable = true; #endif } anv_batch_emit(&cmd_buffer->batch, GENX(PIPELINE_SELECT), ps) { -#if GEN_GEN >= 9 - ps.MaskBits = GEN_GEN >= 12 ? 0x13 : 3; - ps.MediaSamplerDOPClockGateEnable = GEN_GEN >= 12; +#if GFX_VER >= 9 + ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3; + ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12; #endif ps.PipelineSelection = pipeline; } -#if GEN_GEN == 9 +#if GFX_VER == 9 if (devinfo->is_geminilake) { /* Project: DevGLK * @@ -4824,7 +4824,7 @@ genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer) void genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer *cmd_buffer) { - if (GEN_GEN >= 8) + if (GFX_VER >= 8) return; /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER: @@ -4844,7 +4844,7 @@ genX(cmd_buffer_emit_gen7_depth_flush)(struct anv_cmd_buffer *cmd_buffer) } anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pipe) { pipe.DepthCacheFlushEnable = true; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 pipe.TileCacheFlushEnable = true; #endif } @@ -4886,7 +4886,7 @@ genX(cmd_buffer_set_binding_for_gen8_vb_flush)(struct anv_cmd_buffer *cmd_buffer struct anv_address vb_address, uint32_t vb_size) { - if (GEN_GEN < 8 || GEN_GEN > 9 || + if (GFX_VER < 8 || GFX_VER > 9 || !cmd_buffer->device->physical->use_softpin) return; @@ -4934,7 +4934,7 @@ genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)(struct anv_cmd_buffer *cmd_b uint32_t access_type, uint64_t vb_used) { - if (GEN_GEN < 8 || GEN_GEN > 9 || + if (GFX_VER < 8 || GFX_VER > 9 || !cmd_buffer->device->physical->use_softpin) return; @@ -4989,7 +4989,7 @@ genX(cmd_buffer_emit_hashing_mode)(struct anv_cmd_buffer *cmd_buffer, unsigned width, unsigned height, unsigned scale) { -#if GEN_GEN == 9 +#if GFX_VER == 9 const struct gen_device_info *devinfo = &cmd_buffer->device->info; const unsigned slice_hashing[] = { /* Because all Gen9 platforms with more than one slice require @@ -5138,7 +5138,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer) isl_emit_depth_stencil_hiz_s(&device->isl_dev, dw, &info); - if (GEN_GEN >= 12) { + if (GFX_VER >= 12) { cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT; genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); @@ -5211,7 +5211,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top * of each subpass. */ - if (GEN_GEN == 7) + if (GFX_VER == 7) cmd_buffer->state.gfx.vb_dirty |= ~0; /* It is possible to start a render pass with an old pipeline. Because the @@ -5546,7 +5546,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, add_surface_state_relocs(cmd_buffer, *surface_state); - if (GEN_GEN < 10 && + if (GFX_VER < 10 && pass_att->load_op == VK_ATTACHMENT_LOAD_OP_LOAD && iview->image->planes[0].aux_usage != ISL_AUX_USAGE_NONE && iview->planes[0].isl.base_level == 0 && @@ -5558,7 +5558,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, } } -#if GEN_GEN >= 11 +#if GFX_VER >= 11 /* The PIPE_CONTROL command description says: * * "Whenever a Binding Table Index (BTI) used by a Render Taget Message @@ -5572,7 +5572,7 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, ANV_PIPE_STALL_AT_SCOREBOARD_BIT; #endif -#if GEN_GEN == 12 +#if GFX_VER == 12 /* GEN:BUG:14010455700 * * ISL will change some CHICKEN registers depending on the depth surface @@ -5873,7 +5873,7 @@ cmd_buffer_end_subpass(struct anv_cmd_buffer *cmd_buffer) } } -#if GEN_GEN == 7 +#if GFX_VER == 7 /* On gen7, we have to store a texturable version of the stencil buffer in * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and * forth at strategic points. Stencil writes are only allowed in following @@ -5913,7 +5913,7 @@ cmd_buffer_end_subpass(struct anv_cmd_buffer *cmd_buffer) } } } -#endif /* GEN_GEN == 7 */ +#endif /* GFX_VER == 7 */ for (uint32_t i = 0; i < subpass->attachment_count; ++i) { const uint32_t a = subpass->attachments[i].attachment; @@ -6204,7 +6204,7 @@ void genX(CmdWaitEvents)( uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer); for (uint32_t i = 0; i < eventCount; i++) { @@ -6239,7 +6239,7 @@ VkResult genX(CmdSetPerformanceOverrideINTEL)( switch (pOverrideInfo->type) { case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL: { -#if GEN_GEN >= 9 +#if GFX_VER >= 9 anv_batch_write_reg(&cmd_buffer->batch, GENX(CS_DEBUG_MODE2), csdm2) { csdm2._3DRenderingInstructionDisable = pOverrideInfo->enable; csdm2.MediaInstructionDisable = pOverrideInfo->enable; diff --git a/src/intel/vulkan/genX_gpu_memcpy.c b/src/intel/vulkan/genX_gpu_memcpy.c index 5dc79eae05f..eea05a21d42 100644 --- a/src/intel/vulkan/genX_gpu_memcpy.c +++ b/src/intel/vulkan/genX_gpu_memcpy.c @@ -92,7 +92,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, .BufferStartingAddress = src, .BufferPitch = bs, .MOCS = anv_mocs(cmd_buffer->device, src.bo, 0), -#if (GEN_GEN >= 8) +#if (GFX_VER >= 8) .BufferSize = size, #else .EndAddress = anv_address_add(src, size - 1), @@ -112,14 +112,14 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, .Component3Control = (bs >= 16) ? VFCOMP_STORE_SRC : VFCOMP_STORE_0, }); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_INSTANCING), vfi) { vfi.InstancingEnable = false; vfi.VertexElementIndex = 0; } #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs); #endif @@ -135,12 +135,12 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, sbe.VertexURBEntryReadOffset = 1; sbe.NumberofSFOutputAttributes = 1; sbe.VertexURBEntryReadLength = 1; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 sbe.ForceVertexURBEntryReadLength = true; sbe.ForceVertexURBEntryReadOffset = true; #endif -#if GEN_GEN >= 9 +#if GFX_VER >= 9 for (unsigned i = 0; i < 32; i++) sbe.AttributeActiveComponentFormat[i] = ACF_XYZW; #endif @@ -157,7 +157,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, VK_SHADER_STAGE_VERTEX_BIT, entry_size, NULL); anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_SO_BUFFER), sob) { -#if GEN_GEN < 12 +#if GFX_VER < 12 sob.SOBufferIndex = 0; #else sob._3DCommandOpcode = 0; @@ -166,7 +166,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, sob.MOCS = anv_mocs(cmd_buffer->device, dst.bo, 0), sob.SurfaceBaseAddress = dst; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 sob.SOBufferEnable = true; sob.SurfaceSize = size / 4 - 1; #else @@ -174,7 +174,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, sob.SurfaceEndAddress = anv_address_add(dst, size); #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* As SOL writes out data, it updates the SO_WRITE_OFFSET registers with * the end position of the stream. We need to reset this value to 0 at * the beginning of the run or else SOL will start at the offset from @@ -185,7 +185,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, #endif } -#if GEN_GEN <= 7 +#if GFX_VER <= 7 /* The hardware can do this for us on BDW+ (see above) */ anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), load) { load.RegisterOffset = GENX(SO_WRITE_OFFSET0_num); @@ -210,14 +210,14 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, so.RenderingDisable = true; so.Stream0VertexReadOffset = 0; so.Stream0VertexReadLength = DIV_ROUND_UP(32, 64); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 so.Buffer0SurfacePitch = bs; #else so.SOBufferEnable0 = true; #endif } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_TOPOLOGY), topo) { topo.PrimitiveTopologyType = _3DPRIM_POINTLIST; } @@ -227,7 +227,7 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer, vf.StatisticsEnable = false; } -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* Disable Primitive Replication. */ anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr); #endif diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index 846dcf23bd1..f358fe622d3 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -175,7 +175,7 @@ emit_vertex_input(struct anv_graphics_pipeline *pipeline, }; GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* On Broadwell and later, we have a separate VF_INSTANCING packet * that controls instancing. On Haswell and prior, that's part of * VERTEX_BUFFER_STATE which we emit later. @@ -210,7 +210,7 @@ emit_vertex_input(struct anv_graphics_pipeline *pipeline, .SourceElementFormat = ISL_FORMAT_R32G32_UINT, .Component0Control = base_ctrl, .Component1Control = base_ctrl, -#if GEN_GEN >= 8 +#if GFX_VER >= 8 .Component2Control = VFCOMP_STORE_0, .Component3Control = VFCOMP_STORE_0, #else @@ -220,14 +220,14 @@ emit_vertex_input(struct anv_graphics_pipeline *pipeline, }; GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + id_slot * 2], &element); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) { vfi.VertexElementIndex = id_slot; } #endif } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_SGVS), sgvs) { sgvs.VertexIDEnable = vs_prog_data->uses_vertexid; sgvs.VertexIDComponentNumber = 2; @@ -253,7 +253,7 @@ emit_vertex_input(struct anv_graphics_pipeline *pipeline, &p[1 + drawid_slot * 2], &element); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_VF_INSTANCING), vfi) { vfi.VertexElementIndex = drawid_slot; } @@ -332,7 +332,7 @@ emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline) if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) { anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SBE), sbe); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SBE_SWIZ), sbe); #endif return; @@ -349,12 +349,12 @@ emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline) .ConstantInterpolationEnable = wm_prog_data->flat_inputs, }; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 for (unsigned i = 0; i < 32; i++) sbe.AttributeActiveComponentFormat[i] = ACF_XYZW; #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* On Broadwell, they broke 3DSTATE_SBE into two packets */ struct GENX(3DSTATE_SBE_SWIZ) swiz = { GENX(3DSTATE_SBE_SWIZ_header), @@ -421,7 +421,7 @@ emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline) sbe.VertexURBEntryReadOffset = urb_entry_read_offset; sbe.VertexURBEntryReadLength = DIV_ROUND_UP(max_source_attr + 1, 2); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 sbe.ForceVertexURBEntryReadOffset = true; sbe.ForceVertexURBEntryReadLength = true; #endif @@ -432,7 +432,7 @@ emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline) return; GENX(3DSTATE_SBE_pack)(&pipeline->base.batch, dw, &sbe); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 dw = anv_batch_emit_dwords(&pipeline->base.batch, GENX(3DSTATE_SBE_SWIZ_length)); if (!dw) return; @@ -526,7 +526,7 @@ anv_raster_polygon_mode(struct anv_graphics_pipeline *pipeline, } } -#if GEN_GEN <= 7 +#if GFX_VER <= 7 static uint32_t gen7_ms_rast_mode(struct anv_graphics_pipeline *pipeline, const VkPipelineInputAssemblyStateCreateInfo *ia_info, @@ -576,7 +576,7 @@ const uint32_t genX(vk_to_gen_front_face)[] = { [VK_FRONT_FACE_CLOCKWISE] = 0 }; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 static VkConservativeRasterizationModeEXT vk_conservative_rasterization_mode(const VkPipelineRasterizationStateCreateInfo *rs_info) { @@ -615,7 +615,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline, sf.LineStippleEnable = line_info && line_info->stippledLineEnable; #endif -#if GEN_GEN >= 12 +#if GFX_VER >= 12 sf.DerefBlockSize = urb_deref_block_size; #endif @@ -629,7 +629,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline, sf.PointWidth = 1.0; } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 struct GENX(3DSTATE_RASTER) raster = { GENX(3DSTATE_RASTER_header), }; @@ -645,7 +645,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline, /* For details on 3DSTATE_RASTER multisample state, see the BSpec table * "Multisample Modes State". */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 if (raster_mode == VK_POLYGON_MODE_LINE) { /* Unfortunately, configuring our line rasterization hardware on gen8 * and later is rather painful. Instead of giving us bits to tell the @@ -704,15 +704,15 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline, raster.BackFaceFillMode = genX(vk_to_gen_fillmode)[rs_info->polygonMode]; raster.ScissorRectangleEnable = true; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 /* GEN9+ splits ViewportZClipTestEnable into near and far enable bits */ raster.ViewportZFarClipTestEnable = pipeline->depth_clip_enable; raster.ViewportZNearClipTestEnable = pipeline->depth_clip_enable; -#elif GEN_GEN >= 8 +#elif GFX_VER >= 8 raster.ViewportZClipTestEnable = pipeline->depth_clip_enable; #endif -#if GEN_GEN >= 9 +#if GFX_VER >= 9 raster.ConservativeRasterizationEnable = vk_conservative_rasterization_mode(rs_info) != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT; @@ -722,7 +722,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline, raster.GlobalDepthOffsetEnableWireframe = rs_info->depthBiasEnable; raster.GlobalDepthOffsetEnablePoint = rs_info->depthBiasEnable; -#if GEN_GEN == 7 +#if GFX_VER == 7 /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it * can get the depth offsets correct. */ @@ -741,7 +741,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline, } #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf); GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster); #else @@ -765,7 +765,7 @@ emit_ms_state(struct anv_graphics_pipeline *pipeline, * through 3DSTATE_MULTISAMPLE on Gen7/7.5 by passing NULL locations. */ if (pipeline->base.device->vk.enabled_extensions.EXT_sample_locations) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 genX(emit_sample_pattern)(&pipeline->base.batch, pipeline->dynamic_state.sample_locations.samples, pipeline->dynamic_state.sample_locations.locations); @@ -779,7 +779,7 @@ emit_ms_state(struct anv_graphics_pipeline *pipeline, /* On Gen8+ 3DSTATE_MULTISAMPLE does not hold anything we need to modify * for sample locations, so we don't have to emit it dynamically. */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 genX(emit_multisample)(&pipeline->base.batch, info ? info->rasterizationSamples : 1, NULL); @@ -792,7 +792,7 @@ emit_ms_state(struct anv_graphics_pipeline *pipeline, * * 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits. */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 uint32_t sample_mask = 0xffff; #else uint32_t sample_mask = 0xff; @@ -1028,9 +1028,9 @@ emit_ds_state(struct anv_graphics_pipeline *pipeline, const struct anv_render_pass *pass, const struct anv_subpass *subpass) { -#if GEN_GEN == 7 +#if GFX_VER == 7 # define depth_stencil_dw pipeline->gen7.depth_stencil_state -#elif GEN_GEN == 8 +#elif GFX_VER == 8 # define depth_stencil_dw pipeline->gen8.wm_depth_stencil #else # define depth_stencil_dw pipeline->gen9.wm_depth_stencil @@ -1066,7 +1066,7 @@ emit_ds_state(struct anv_graphics_pipeline *pipeline, bool dynamic_stencil_op = dynamic_states & ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP; -#if GEN_GEN <= 7 +#if GFX_VER <= 7 struct GENX(DEPTH_STENCIL_STATE) depth_stencil = { #else struct GENX(3DSTATE_WM_DEPTH_STENCIL) depth_stencil = { @@ -1110,7 +1110,7 @@ emit_ds_state(struct anv_graphics_pipeline *pipeline, depth_stencil.BackfaceStencilTestFunction = 0; } -#if GEN_GEN <= 7 +#if GFX_VER <= 7 GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil); #else GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, depth_stencil_dw, &depth_stencil); @@ -1135,7 +1135,7 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline, const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline); struct GENX(BLEND_STATE) blend_state = { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable, .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable, #endif @@ -1156,7 +1156,7 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline, bool has_writeable_rt = false; uint32_t *state_pos = pipeline->blend_state.map; state_pos += GENX(BLEND_STATE_length); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 struct GENX(BLEND_STATE_ENTRY) bs0 = { 0 }; #endif for (unsigned i = 0; i < surface_count; i++) { @@ -1186,7 +1186,7 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline, &info->pAttachments[binding->index]; struct GENX(BLEND_STATE_ENTRY) entry = { -#if GEN_GEN < 8 +#if GFX_VER < 8 .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable, .AlphaToOneEnable = ms_info && ms_info->alphaToOneEnable, #endif @@ -1226,7 +1226,7 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline, if (a->srcColorBlendFactor != a->srcAlphaBlendFactor || a->dstColorBlendFactor != a->dstAlphaBlendFactor || a->colorBlendOp != a->alphaBlendOp) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 blend_state.IndependentAlphaBlendEnable = true; #else entry.IndependentAlphaBlendEnable = true; @@ -1278,13 +1278,13 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline, } GENX(BLEND_STATE_ENTRY_pack)(NULL, state_pos, &entry); state_pos += GENX(BLEND_STATE_ENTRY_length); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 if (i == 0) bs0 = entry; #endif } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS_BLEND), blend) { blend.AlphaToCoverageEnable = blend_state.AlphaToCoverageEnable; blend.HasWriteableRT = has_writeable_rt; @@ -1305,7 +1305,7 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline, anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_BLEND_STATE_POINTERS), bsp) { bsp.BlendStatePointer = pipeline->blend_state.offset; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 bsp.BlendStatePointerValid = true; #endif } @@ -1339,7 +1339,7 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline, anv_raster_polygon_mode(pipeline, ia_info, rs_info); clip.ViewportXYClipTestEnable = (raster_mode == VK_POLYGON_MODE_FILL); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 clip.VertexSubPixelPrecisionSelect = _8Bit; #endif clip.ClipMode = CLIPMODE_NORMAL; @@ -1376,7 +1376,7 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline, clip.ForceZeroRTAIndexEnable = !(last->vue_map.slots_valid & VARYING_BIT_LAYER); -#if GEN_GEN == 7 +#if GFX_VER == 7 clip.FrontWinding = genX(vk_to_gen_front_face)[rs_info->frontFace]; clip.CullMode = genX(vk_to_gen_cullmode)[rs_info->cullMode]; clip.ViewportZClipTestEnable = pipeline->depth_clip_enable; @@ -1419,7 +1419,7 @@ emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline, so.RenderStreamSelect = stream_info ? stream_info->rasterizationStream : 0; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 so.Buffer0SurfacePitch = xfb_info->buffers[0].stride; so.Buffer1SurfacePitch = xfb_info->buffers[1].stride; so.Buffer2SurfacePitch = xfb_info->buffers[2].stride; @@ -1606,13 +1606,13 @@ emit_3dstate_vs(struct anv_graphics_pipeline *pipeline) vs.Enable = true; vs.StatisticsEnable = true; vs.KernelStartPointer = vs_bin->kernel.offset; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 vs.SIMD8DispatchEnable = vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8; #endif assert(!vs_prog_data->base.base.use_alt_mode); -#if GEN_GEN < 11 +#if GFX_VER < 11 vs.SingleVertexDispatch = false; #endif vs.VectorMaskEnable = false; @@ -1621,14 +1621,14 @@ emit_3dstate_vs(struct anv_graphics_pipeline *pipeline) * Disable the Sampler state prefetch functionality in the SARB by * programming 0xB000[30] to '1'. */ - vs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(vs_bin); + vs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(vs_bin); vs.BindingTableEntryCount = vs_bin->bind_map.surface_count; vs.FloatingPointMode = IEEE754; vs.IllegalOpcodeExceptionEnable = false; vs.SoftwareExceptionEnable = false; vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1; - if (GEN_GEN == 9 && devinfo->gt == 4 && + if (GFX_VER == 9 && devinfo->gt == 4 && anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL)) { /* On Sky Lake GT4, we have experienced some hangs related to the VS * cache and tessellation. It is unknown exactly what is happening @@ -1655,7 +1655,7 @@ emit_3dstate_vs(struct anv_graphics_pipeline *pipeline) vs.DispatchGRFStartRegisterForURBData = vs_prog_data->base.base.dispatch_grf_start_reg; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 vs.UserClipDistanceClipTestEnableBitmask = vs_prog_data->base.clip_distance_mask; vs.UserClipDistanceCullTestEnableBitmask = @@ -1693,10 +1693,10 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline, hs.StatisticsEnable = true; hs.KernelStartPointer = tcs_bin->kernel.offset; /* WA_1606682166 */ - hs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(tcs_bin); + hs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tcs_bin); hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* GEN:BUG:1604578095: * * Hang occurs when the number of max threads is less than 2 times @@ -1714,7 +1714,7 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline, hs.VertexURBEntryReadOffset = 0; hs.DispatchGRFStartRegisterForURBData = tcs_prog_data->base.base.dispatch_grf_start_reg & 0x1f; -#if GEN_GEN >= 12 +#if GFX_VER >= 12 hs.DispatchGRFStartRegisterForURBData5 = tcs_prog_data->base.base.dispatch_grf_start_reg >> 5; #endif @@ -1724,14 +1724,14 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline, hs.ScratchSpaceBasePointer = get_scratch_address(&pipeline->base, MESA_SHADER_TESS_CTRL, tcs_bin); -#if GEN_GEN == 12 +#if GFX_VER == 12 /* Patch Count threshold specifies the maximum number of patches that * will be accumulated before a thread dispatch is forced. */ hs.PatchCountThreshold = tcs_prog_data->patch_count_threshold; #endif -#if GEN_GEN >= 9 +#if GFX_VER >= 9 hs.DispatchMode = tcs_prog_data->base.dispatch_mode; hs.IncludePrimitiveID = tcs_prog_data->include_primitive_id; #endif @@ -1771,7 +1771,7 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline, ds.StatisticsEnable = true; ds.KernelStartPointer = tes_bin->kernel.offset; /* WA_1606682166 */ - ds.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(tes_bin); + ds.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tes_bin); ds.BindingTableEntryCount = tes_bin->bind_map.surface_count; ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1; @@ -1783,8 +1783,8 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline, ds.DispatchGRFStartRegisterForURBData = tes_prog_data->base.base.dispatch_grf_start_reg; -#if GEN_GEN >= 8 -#if GEN_GEN < 11 +#if GFX_VER >= 8 +#if GFX_VER < 11 ds.DispatchMode = tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8 ? DISPATCH_MODE_SIMD8_SINGLE_PATCH : @@ -1829,12 +1829,12 @@ emit_3dstate_gs(struct anv_graphics_pipeline *pipeline) gs.SingleProgramFlow = false; gs.VectorMaskEnable = false; /* WA_1606682166 */ - gs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(gs_bin); + gs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(gs_bin); gs.BindingTableEntryCount = gs_bin->bind_map.surface_count; gs.IncludeVertexHandles = gs_prog_data->base.include_vue_handles; gs.IncludePrimitiveID = gs_prog_data->include_primitive_id; - if (GEN_GEN == 8) { + if (GFX_VER == 8) { /* Broadwell is weird. It needs us to divide by 2. */ gs.MaximumNumberofThreads = devinfo->max_gs_threads / 2 - 1; } else { @@ -1849,7 +1849,7 @@ emit_3dstate_gs(struct anv_graphics_pipeline *pipeline) gs.InstanceControl = MAX2(gs_prog_data->invocations, 1) - 1; gs.ReorderMode = TRAILING; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 gs.ExpectedVertexCount = gs_prog_data->vertices_in; gs.StaticOutput = gs_prog_data->static_vertex_count >= 0; gs.StaticOutputVertexCount = gs_prog_data->static_vertex_count >= 0 ? @@ -1861,7 +1861,7 @@ emit_3dstate_gs(struct anv_graphics_pipeline *pipeline) gs.DispatchGRFStartRegisterForURBData = gs_prog_data->base.base.dispatch_grf_start_reg; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 gs.UserClipDistanceClipTestEnableBitmask = gs_prog_data->base.clip_distance_mask; gs.UserClipDistanceCullTestEnableBitmask = @@ -1925,7 +1925,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline, struct anv_subpass *subp wm.EarlyDepthStencilControl = EDSC_NORMAL; } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* Gen8 hardware tries to compute ThreadDispatchEnable for us but * doesn't take into account KillPixels when no depth or stencil * writes are enabled. In order for occlusion queries to work @@ -1950,7 +1950,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline, struct anv_subpass *subp wm.BarycentricInterpolationMode = wm_prog_data->barycentric_interp_modes; -#if GEN_GEN < 8 +#if GFX_VER < 8 wm.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode; wm.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth; wm.PixelShaderUsesSourceW = wm_prog_data->uses_src_w; @@ -2001,7 +2001,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline, if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) { anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS), ps) { -#if GEN_GEN == 7 +#if GFX_VER == 7 /* Even if no fragments are ever dispatched, gen7 hardware hangs if * we don't at least set the maximum number of threads. */ @@ -2013,7 +2013,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline, const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline); -#if GEN_GEN < 8 +#if GFX_VER < 8 /* The hardware wedges if you have this bit set but don't turn on any dual * source blend factors. */ @@ -2048,7 +2048,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline, * Since 16x MSAA is first introduced on SKL, we don't need to apply * the workaround on any older hardware. */ - if (GEN_GEN >= 9 && !wm_prog_data->persample_dispatch && + if (GFX_VER >= 9 && !wm_prog_data->persample_dispatch && multisample && multisample->rasterizationSamples == 16) { assert(ps._8PixelDispatchEnable || ps._16PixelDispatchEnable); ps._32PixelDispatchEnable = false; @@ -2062,15 +2062,15 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline, brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2); ps.SingleProgramFlow = false; - ps.VectorMaskEnable = GEN_GEN >= 8; + ps.VectorMaskEnable = GFX_VER >= 8; /* WA_1606682166 */ - ps.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(fs_bin); + ps.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(fs_bin); ps.BindingTableEntryCount = fs_bin->bind_map.surface_count; ps.PushConstantEnable = wm_prog_data->base.nr_params > 0 || wm_prog_data->base.ubo_ranges[0].length; ps.PositionXYOffsetSelect = wm_prog_data->uses_pos_offset ? POSOFFSET_SAMPLE: POSOFFSET_NONE; -#if GEN_GEN < 8 +#if GFX_VER < 8 ps.AttributeEnable = wm_prog_data->num_varying_inputs > 0; ps.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask; ps.DualSourceBlendEnable = dual_src_blend; @@ -2083,9 +2083,9 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline, ps.SampleMask = 0xff; #endif -#if GEN_GEN >= 9 +#if GFX_VER >= 9 ps.MaximumNumberofThreadsPerPSD = 64 - 1; -#elif GEN_GEN >= 8 +#elif GFX_VER >= 8 ps.MaximumNumberofThreadsPerPSD = 64 - 2; #else ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1; @@ -2104,7 +2104,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline, } } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 static void emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline, struct anv_subpass *subpass, @@ -2135,7 +2135,7 @@ emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline, ps.PixelShaderKillsPixel = subpass->has_ds_self_dep || wm_prog_data->uses_kill; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil; ps.PixelShaderPullsBary = wm_prog_data->pulls_bary; @@ -2205,7 +2205,7 @@ compute_kill_pixel(struct anv_graphics_pipeline *pipeline, (ms_info && ms_info->alphaToCoverageEnable); } -#if GEN_GEN == 12 +#if GFX_VER == 12 static void emit_3dstate_primitive_replication(struct anv_graphics_pipeline *pipeline) { @@ -2319,7 +2319,7 @@ genX(graphics_pipeline_create)( dynamic_states); emit_3dstate_streamout(pipeline, pCreateInfo->pRasterizationState); -#if GEN_GEN == 12 +#if GFX_VER == 12 emit_3dstate_primitive_replication(pipeline); #endif @@ -2351,7 +2351,7 @@ genX(graphics_pipeline_create)( pCreateInfo->pRasterizationState, cb_info, ms_info, line_info); emit_3dstate_ps(pipeline, cb_info, ms_info); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 emit_3dstate_ps_extra(pipeline, subpass, pCreateInfo->pRasterizationState); @@ -2414,25 +2414,25 @@ emit_compute_state(struct anv_compute_pipeline *pipeline, const struct gen_device_info *devinfo = &device->info; anv_batch_emit(&pipeline->base.batch, GENX(MEDIA_VFE_STATE), vfe) { -#if GEN_GEN > 7 +#if GFX_VER > 7 vfe.StackSize = 0; #else vfe.GPGPUMode = true; #endif vfe.MaximumNumberofThreads = devinfo->max_cs_threads * subslices - 1; - vfe.NumberofURBEntries = GEN_GEN <= 7 ? 0 : 2; -#if GEN_GEN < 11 + vfe.NumberofURBEntries = GFX_VER <= 7 ? 0 : 2; +#if GFX_VER < 11 vfe.ResetGatewayTimer = true; #endif -#if GEN_GEN <= 8 +#if GFX_VER <= 8 vfe.BypassGatewayControl = true; #endif - vfe.URBEntryAllocationSize = GEN_GEN <= 7 ? 0 : 2; + vfe.URBEntryAllocationSize = GFX_VER <= 7 ? 0 : 2; vfe.CURBEAllocationSize = vfe_curbe_allocation; if (cs_bin->prog_data->total_scratch) { - if (GEN_GEN >= 8) { + if (GFX_VER >= 8) { /* Broadwell's Per Thread Scratch Space is in the range [0, 11] * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M. */ @@ -2462,14 +2462,14 @@ emit_compute_state(struct anv_compute_pipeline *pipeline, brw_cs_prog_data_prog_offset(cs_prog_data, cs_params.simd_size), /* WA_1606682166 */ - .SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(cs_bin), + .SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(cs_bin), /* We add 1 because the CS indirect parameters buffer isn't accounted * for in bind_map.surface_count. */ .BindingTableEntryCount = 1 + MIN2(cs_bin->bind_map.surface_count, 30), .BarrierEnable = cs_prog_data->uses_barrier, .SharedLocalMemorySize = - encode_slm_size(GEN_GEN, cs_prog_data->base.total_shared), + encode_slm_size(GFX_VER, cs_prog_data->base.total_shared), #if GFX_VERx10 != 75 .ConstantURBEntryReadOffset = 0, @@ -2479,7 +2479,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline, .CrossThreadConstantDataReadLength = cs_prog_data->push.cross_thread.regs, #endif -#if GEN_GEN >= 12 +#if GFX_VER >= 12 /* TODO: Check if we are missing workarounds and enable mid-thread * preemption. * diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c index 750731af6bf..d10dead610c 100644 --- a/src/intel/vulkan/genX_query.c +++ b/src/intel/vulkan/genX_query.c @@ -37,7 +37,7 @@ * - GPR 15 for conditional rendering */ #define MI_BUILDER_NUM_ALLOC_GPRS 14 -#define MI_BUILDER_CAN_WRITE_BATCH GEN_GEN >= 8 +#define MI_BUILDER_CAN_WRITE_BATCH GFX_VER >= 8 #define __gen_get_batch_dwords anv_batch_emit_dwords #define __gen_address_offset anv_address_add #define __gen_get_batch_address(b, a) anv_batch_address(b, a) @@ -65,7 +65,7 @@ VkResult genX(CreateQueryPool)( { ANV_FROM_HANDLE(anv_device, device, _device); const struct anv_physical_device *pdevice = device->physical; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 const VkQueryPoolPerformanceCreateInfoKHR *perf_query_info = NULL; struct gen_perf_counter_pass *counter_pass; struct gen_perf_query_info **pass_query; @@ -130,7 +130,7 @@ VkResult genX(CreateQueryPool)( uint64s_per_slot += 2 * DIV_ROUND_UP(layout->size, sizeof(uint64_t)); break; } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: { const struct gen_perf_query_field_layout *layout = &pdevice->perf->query_layout; @@ -176,7 +176,7 @@ VkResult genX(CreateQueryPool)( pool->data_offset = data_offset; pool->snapshot_size = (pool->stride - data_offset) / 2; } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 else if (pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR) { pool->pass_size = pool->stride / n_passes; pool->data_offset = data_offset; @@ -215,7 +215,7 @@ VkResult genX(CreateQueryPool)( if (result != VK_SUCCESS) goto fail; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 if (pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR) { for (uint32_t p = 0; p < pool->n_passes; p++) { struct mi_builder b; @@ -259,7 +259,7 @@ void genX(DestroyQueryPool)( vk_free2(&device->vk.alloc, pAllocator, pool); } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /** * VK_KHR_performance_query layout : * @@ -409,7 +409,7 @@ query_slot(struct anv_query_pool *pool, uint32_t query) static bool query_is_available(struct anv_query_pool *pool, uint32_t query) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 if (pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR) { for (uint32_t p = 0; p < pool->n_passes; p++) { volatile uint64_t *slot = @@ -558,7 +558,7 @@ VkResult genX(GetQueryPoolResults)( break; } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: { const struct anv_physical_device *pdevice = device->physical; assert((flags & (VK_QUERY_RESULT_WITH_AVAILABILITY_BIT | @@ -627,7 +627,7 @@ emit_ps_depth_count(struct anv_cmd_buffer *cmd_buffer, pc.DepthStallEnable = true; pc.Address = addr; - if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4) + if (GFX_VER == 9 && cmd_buffer->device->info.gt == 4) pc.CommandStreamerStallEnable = true; } } @@ -696,7 +696,7 @@ emit_zero_queries(struct anv_cmd_buffer *cmd_buffer, } break; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: { for (uint32_t i = 0; i < num_queries; i++) { for (uint32_t p = 0; p < pool->n_passes; p++) { @@ -754,7 +754,7 @@ void genX(CmdResetQueryPool)( break; } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: { struct mi_builder b; mi_builder_init(&b, &cmd_buffer->device->info, &cmd_buffer->batch); @@ -795,7 +795,7 @@ void genX(ResetQueryPool)( for (uint32_t i = 0; i < queryCount; i++) { if (pool->type == VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 for (uint32_t p = 0; p < pool->n_passes; p++) { uint64_t *pass_slot = pool->bo->map + khr_perf_query_availability_offset(pool, firstQuery + i, p); @@ -943,7 +943,7 @@ void genX(CmdBeginQueryIndexedEXT)( emit_xfb_query(&b, index, anv_address_add(query_addr, 8)); break; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: { if (!khr_perf_query_ensure_relocs(cmd_buffer)) return; @@ -1125,7 +1125,7 @@ void genX(CmdEndQueryIndexedEXT)( emit_query_mi_availability(&b, query_addr, true); break; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: { anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { pc.CommandStreamerStallEnable = true; @@ -1270,7 +1270,7 @@ void genX(CmdWriteTimestamp)( pc.PostSyncOperation = WriteTimestamp; pc.Address = anv_address_add(query_addr, 8); - if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4) + if (GFX_VER == 9 && cmd_buffer->device->info.gt == 4) pc.CommandStreamerStallEnable = true; } break; @@ -1454,7 +1454,7 @@ void genX(CmdCopyQueryPoolResults)( gpu_write_query_result(&b, dest_addr, flags, 0, result); break; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 case VK_QUERY_TYPE_PERFORMANCE_QUERY_KHR: unreachable("Copy KHR performance query results not implemented"); break; diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 8cd59d4fe4d..9d1a2a2da9c 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -81,7 +81,7 @@ genX(emit_slice_hashing_state)(struct anv_device *device, { device->slice_hash = (struct anv_state) { 0 }; -#if GEN_GEN == 11 +#if GFX_VER == 11 assert(device->info.ppipe_subslices[2] == 0); if (device->info.ppipe_subslices[0] == device->info.ppipe_subslices[1]) @@ -163,14 +163,14 @@ init_render_queue_state(struct anv_queue *queue) batch.end = (void *) cmds + sizeof(cmds); anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) { -#if GEN_GEN >= 9 - ps.MaskBits = GEN_GEN >= 12 ? 0x13 : 3; - ps.MediaSamplerDOPClockGateEnable = GEN_GEN >= 12; +#if GFX_VER >= 9 + ps.MaskBits = GFX_VER >= 12 ? 0x13 : 3; + ps.MediaSamplerDOPClockGateEnable = GFX_VER >= 12; #endif ps.PipelineSelection = _3D; } -#if GEN_GEN == 9 +#if GFX_VER == 9 anv_batch_write_reg(&batch, GENX(CACHE_MODE_1), cm1) { cm1.FloatBlendOptimizationEnable = true; cm1.FloatBlendOptimizationEnableMask = true; @@ -192,7 +192,7 @@ init_render_queue_state(struct anv_queue *queue) rect.DrawingRectangleOriginX = 0; } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck); genX(emit_sample_pattern)(&batch, 0, NULL); @@ -208,7 +208,7 @@ init_render_queue_state(struct anv_queue *queue) anv_batch_emit(&batch, GENX(3DSTATE_WM_HZ_OP), hzp); #endif -#if GEN_GEN == 11 +#if GFX_VER == 11 /* The default behavior of bit 5 "Headerless Message for Pre-emptable * Contexts" in SAMPLER MODE register is set to 0, which means * headerless sampler messages are not allowed for pre-emptable @@ -236,7 +236,7 @@ init_render_queue_state(struct anv_queue *queue) #endif genX(emit_slice_hashing_state)(device, &batch); -#if GEN_GEN >= 11 +#if GFX_VER >= 11 /* hardware specification recommends disabling repacking for * the compatibility with decompression mechanism in display controller. */ @@ -258,7 +258,7 @@ init_render_queue_state(struct anv_queue *queue) } #endif -#if GEN_GEN == 12 +#if GFX_VER == 12 if (device->info.has_aux_map) { uint64_t aux_base_addr = intel_aux_map_get_base(device->aux_map_ctx); assert(aux_base_addr % (32 * 1024) == 0); @@ -278,13 +278,13 @@ init_render_queue_state(struct anv_queue *queue) * * This is only safe on kernels with context isolation support. */ - if (GEN_GEN >= 8 && device->physical->has_context_isolation) { -#if GEN_GEN >= 9 + if (GFX_VER >= 8 && device->physical->has_context_isolation) { +#if GFX_VER >= 9 anv_batch_write_reg(&batch, GENX(CS_DEBUG_MODE2), csdm2) { csdm2.CONSTANT_BUFFERAddressOffsetDisable = true; csdm2.CONSTANT_BUFFERAddressOffsetDisableMask = true; } -#elif GEN_GEN == 8 +#elif GFX_VER == 8 anv_batch_write_reg(&batch, GENX(INSTPM), instpm) { instpm.CONSTANT_BUFFERAddressOffsetDisable = true; instpm.CONSTANT_BUFFERAddressOffsetDisableMask = true; @@ -292,7 +292,7 @@ init_render_queue_state(struct anv_queue *queue) #endif } -#if GEN_GEN >= 11 +#if GFX_VER >= 11 /* Starting with GFX version 11, SLM is no longer part of the L3$ config * so it never changes throughout the lifetime of the VkDevice. */ @@ -343,9 +343,9 @@ genX(emit_l3_config)(struct anv_batch *batch, { UNUSED const struct gen_device_info *devinfo = &device->info; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 -#if GEN_GEN >= 12 +#if GFX_VER >= 12 #define L3_ALLOCATION_REG GENX(L3ALLOC) #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num) #else @@ -355,23 +355,23 @@ genX(emit_l3_config)(struct anv_batch *batch, anv_batch_write_reg(batch, L3_ALLOCATION_REG, l3cr) { if (cfg == NULL) { -#if GEN_GEN >= 12 +#if GFX_VER >= 12 l3cr.L3FullWayAllocationEnable = true; #else unreachable("Invalid L3$ config"); #endif } else { -#if GEN_GEN < 11 +#if GFX_VER < 11 l3cr.SLMEnable = cfg->n[INTEL_L3P_SLM]; #endif -#if GEN_GEN == 11 +#if GFX_VER == 11 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be * set in L3CNTLREG register. The default setting of the bit is not * the desirable behavior. */ l3cr.ErrorDetectionBehaviorControl = true; l3cr.UseFullWays = true; -#endif /* GEN_GEN == 11 */ +#endif /* GFX_VER == 11 */ assert(cfg->n[INTEL_L3P_IS] == 0); assert(cfg->n[INTEL_L3P_C] == 0); assert(cfg->n[INTEL_L3P_T] == 0); @@ -382,7 +382,7 @@ genX(emit_l3_config)(struct anv_batch *batch, } } -#else /* GEN_GEN < 8 */ +#else /* GFX_VER < 8 */ const bool has_dc = cfg->n[INTEL_L3P_DC] || cfg->n[INTEL_L3P_ALL]; const bool has_is = cfg->n[INTEL_L3P_IS] || cfg->n[INTEL_L3P_RO] || @@ -455,7 +455,7 @@ genX(emit_l3_config)(struct anv_batch *batch, } #endif /* GFX_VERx10 == 75 */ -#endif /* GEN_GEN < 8 */ +#endif /* GFX_VER < 8 */ } void @@ -466,7 +466,7 @@ genX(emit_multisample)(struct anv_batch *batch, uint32_t samples, ms.NumberofMultisamples = __builtin_ffs(samples) - 1; ms.PixelLocation = CENTER; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* The PRM says that this bit is valid only for DX9: * * SW can choose to set this bit only for DX9 API. DX10/OGL API's @@ -514,7 +514,7 @@ genX(emit_multisample)(struct anv_batch *batch, uint32_t samples, } } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 void genX(emit_sample_pattern)(struct anv_batch *batch, uint32_t samples, const VkSampleLocationEXT *locations) @@ -555,7 +555,7 @@ genX(emit_sample_pattern)(struct anv_batch *batch, uint32_t samples, case 8: INTEL_SAMPLE_POS_8X_ARRAY(sp._8xSample, locations); break; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 case 16: INTEL_SAMPLE_POS_16X_ARRAY(sp._16xSample, locations); break; @@ -568,7 +568,7 @@ genX(emit_sample_pattern)(struct anv_batch *batch, uint32_t samples, INTEL_SAMPLE_POS_2X(sp._2xSample); INTEL_SAMPLE_POS_4X(sp._4xSample); INTEL_SAMPLE_POS_8X(sp._8xSample); -#if GEN_GEN >= 9 +#if GFX_VER >= 9 INTEL_SAMPLE_POS_16X(sp._16xSample); #endif } @@ -630,7 +630,7 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = { [VK_COMPARE_OP_ALWAYS] = PREFILTEROPNEVER, }; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 static const uint32_t vk_to_gen_sampler_reduction_mode[] = { [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER, [VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM, @@ -665,13 +665,13 @@ VkResult genX(CreateSampler)( pCreateInfo->borderColor * border_color_stride; } else { - assert(GEN_GEN >= 8); + assert(GFX_VER >= 8); sampler->custom_border_color = anv_state_reserved_pool_alloc(&device->custom_border_colors); border_color_offset = sampler->custom_border_color.offset; } -#if GEN_GEN >= 9 +#if GFX_VER >= 9 unsigned sampler_reduction_mode = STD_FILTER; bool enable_sampler_reduction = false; #endif @@ -696,7 +696,7 @@ VkResult genX(CreateSampler)( sampler->conversion = conversion; break; } -#if GEN_GEN >= 9 +#if GFX_VER >= 9 case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO: { VkSamplerReductionModeCreateInfo *sampler_reduction = (VkSamplerReductionModeCreateInfo *) ext; @@ -772,13 +772,13 @@ VkResult genX(CreateSampler)( .SamplerDisable = false, .TextureBorderColorMode = DX10OGL, -#if GEN_GEN >= 8 +#if GFX_VER >= 8 .LODPreClampMode = CLAMP_MODE_OGL, #else .LODPreClampEnable = CLAMP_ENABLE_OGL, #endif -#if GEN_GEN == 8 +#if GFX_VER == 8 .BaseMipLevel = 0.0, #endif .MipModeFilter = mip_filter_mode, @@ -799,7 +799,7 @@ VkResult genX(CreateSampler)( .BorderColorPointer = border_color_offset, -#if GEN_GEN >= 8 +#if GFX_VER >= 8 .LODClampMagnificationMode = MIPNONE, #endif @@ -816,7 +816,7 @@ VkResult genX(CreateSampler)( .TCYAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeV], .TCZAddressControlMode = vk_to_gen_tex_address[pCreateInfo->addressModeW], -#if GEN_GEN >= 9 +#if GFX_VER >= 9 .ReductionType = sampler_reduction_mode, .ReductionTypeEnable = enable_sampler_reduction, #endif diff --git a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h index d279094a5a2..62a008efc41 100644 --- a/src/mesa/drivers/dri/i965/gen4_blorp_exec.h +++ b/src/mesa/drivers/dri/i965/gen4_blorp_exec.h @@ -55,7 +55,7 @@ blorp_emit_vs_state(struct blorp_batch *batch) blorp_emit_dynamic(batch, GENX(VS_STATE), vs, 64, &offset) { vs.Enable = false; vs.URBEntryAllocationSize = brw->urb.vsize - 1; -#if GEN_GEN == 5 +#if GFX_VER == 5 vs.NumberofURBEntries = brw->urb.nr_vs_entries >> 2; #else vs.NumberofURBEntries = brw->urb.nr_vs_entries; @@ -75,7 +75,7 @@ blorp_emit_sf_state(struct blorp_batch *batch, uint32_t offset; blorp_emit_dynamic(batch, GENX(SF_STATE), sf, 64, &offset) { -#if GEN_GEN == 4 +#if GFX_VER == 4 sf.KernelStartPointer = instruction_state_address(batch, params->sf_prog_kernel); #else @@ -89,7 +89,7 @@ blorp_emit_sf_state(struct blorp_batch *batch, sf.URBEntryAllocationSize = brw->urb.sfsize - 1; sf.NumberofURBEntries = brw->urb.nr_sf_entries; -#if GEN_GEN == 5 +#if GFX_VER == 5 sf.MaximumNumberofThreads = MIN2(48, brw->urb.nr_sf_entries) - 1; #else sf.MaximumNumberofThreads = MIN2(24, brw->urb.nr_sf_entries) - 1; @@ -113,7 +113,7 @@ blorp_emit_wm_state(struct blorp_batch *batch, blorp_emit_dynamic(batch, GENX(WM_STATE), wm, 64, &offset) { if (params->src.enabled) { /* Iron Lake can't do sampler prefetch */ - wm.SamplerCount = (GEN_GEN != 5); + wm.SamplerCount = (GFX_VER != 5); wm.BindingTableEntryCount = 2; uint32_t sampler = blorp_emit_sampler_state(batch); wm.SamplerStatePointer = dynamic_state_address(batch, sampler); @@ -134,7 +134,7 @@ blorp_emit_wm_state(struct blorp_batch *batch, wm._16PixelDispatchEnable = prog_data->dispatch_16; wm._32PixelDispatchEnable = prog_data->dispatch_32; -#if GEN_GEN == 4 +#if GFX_VER == 4 wm.KernelStartPointer0 = instruction_state_address(batch, params->wm_prog_kernel); wm.GRFRegisterCount0 = brw_wm_prog_data_reg_blocks(prog_data, wm, 0); diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c index 198d6b7c660..e5dc61cc796 100644 --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c @@ -32,7 +32,7 @@ #include "blorp/blorp_genX_exec.h" -#if GEN_GEN <= 5 +#if GFX_VER <= 5 #include "gen4_blorp_exec.h" #endif @@ -62,7 +62,7 @@ blorp_emit_reloc(struct blorp_batch *batch, struct brw_context *brw = batch->driver_batch; uint32_t offset; - if (GEN_GEN < 6 && brw_ptr_in_state_buffer(&brw->batch, location)) { + if (GFX_VER < 6 && brw_ptr_in_state_buffer(&brw->batch, location)) { offset = (char *)location - (char *)brw->batch.state.map; return brw_state_reloc(&brw->batch, offset, address.buffer, address.offset + delta, @@ -90,7 +90,7 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset, address.reloc_flags); void *reloc_ptr = (void *)brw->batch.state.map + ss_offset; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 *(uint64_t *)reloc_ptr = reloc_val; #else *(uint32_t *)reloc_ptr = reloc_val; @@ -105,7 +105,7 @@ blorp_get_surface_address(UNUSED struct blorp_batch *blorp_batch, return 0ull; } -#if GEN_GEN >= 7 && GEN_GEN < 10 +#if GFX_VER >= 7 && GFX_VER < 10 static struct blorp_address blorp_get_surface_base_address(struct blorp_batch *batch) { @@ -186,17 +186,17 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size, */ .reloc_flags = RELOC_32BIT, -#if GEN_GEN == 11 +#if GFX_VER == 11 .mocs = ICL_MOCS_WB, -#elif GEN_GEN == 10 +#elif GFX_VER == 10 .mocs = CNL_MOCS_WB, -#elif GEN_GEN == 9 +#elif GFX_VER == 9 .mocs = SKL_MOCS_WB, -#elif GEN_GEN == 8 +#elif GFX_VER == 8 .mocs = BDW_MOCS_WB, -#elif GEN_GEN == 7 +#elif GFX_VER == 7 .mocs = GEN7_MOCS_L3, -#elif GEN_GEN > 6 +#elif GFX_VER > 6 #error "Missing MOCS setting!" #endif }; @@ -213,7 +213,7 @@ blorp_vf_invalidate_for_vb_48b_transitions(UNUSED struct blorp_batch *batch, UNUSED uint32_t *sizes, UNUSED unsigned num_vbs) { -#if GEN_GEN >= 8 && GEN_GEN < 11 +#if GFX_VER >= 8 && GFX_VER < 11 struct brw_context *brw = batch->driver_batch; bool need_invalidate = false; @@ -255,7 +255,7 @@ blorp_flush_range(UNUSED struct blorp_batch *batch, UNUSED void *start, */ } -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static const struct intel_l3_config * blorp_get_l3_config(struct blorp_batch *batch) { @@ -264,7 +264,7 @@ blorp_get_l3_config(struct blorp_batch *batch) return brw->l3.config; } -#else /* GEN_GEN < 7 */ +#else /* GFX_VER < 7 */ static void blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size, @@ -273,7 +273,7 @@ blorp_emit_urb_config(struct blorp_batch *batch, assert(batch->blorp->driver_ctx == batch->driver_batch); struct brw_context *brw = batch->driver_batch; -#if GEN_GEN == 6 +#if GFX_VER == 6 gen6_upload_urb(brw, vs_entry_size, false, 0); #else /* We calculate it now and emit later. */ @@ -291,7 +291,7 @@ genX(blorp_exec)(struct blorp_batch *batch, struct gl_context *ctx = &brw->ctx; bool check_aperture_failed_once = false; -#if GEN_GEN >= 11 +#if GFX_VER >= 11 /* The PIPE_CONTROL command description says: * * "Whenever a Binding Table Index (BTI) used by a Render Taget Message @@ -334,22 +334,22 @@ retry: check_aperture_failed_once |= brw_batch_saved_state_is_empty(brw); brw->batch.no_wrap = true; -#if GEN_GEN == 6 +#if GFX_VER == 6 /* Emit workaround flushes when we switch from drawing to blorping. */ brw_emit_post_sync_nonzero_flush(brw); #endif brw_upload_state_base_address(brw); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 gen7_l3_state.emit(brw); #endif -#if GEN_GEN >= 6 +#if GFX_VER >= 6 brw_emit_depth_stall_flushes(brw); #endif -#if GEN_GEN == 8 +#if GFX_VER == 8 gen8_write_pma_stall_bits(brw, 0); #endif diff --git a/src/mesa/drivers/dri/i965/genX_boilerplate.h b/src/mesa/drivers/dri/i965/genX_boilerplate.h index b4567df6d5e..20df05d0a3a 100644 --- a/src/mesa/drivers/dri/i965/genX_boilerplate.h +++ b/src/mesa/drivers/dri/i965/genX_boilerplate.h @@ -59,7 +59,7 @@ __gen_combine_address(struct brw_context *brw, void *location, if (address.bo == NULL) { return address.offset + delta; } else { - if (GEN_GEN < 6 && brw_ptr_in_state_buffer(batch, location)) { + if (GFX_VER < 6 && brw_ptr_in_state_buffer(batch, location)) { offset = (char *) location - (char *) brw->batch.state.map; return brw_state_reloc(batch, offset, address.bo, address.offset + delta, diff --git a/src/mesa/drivers/dri/i965/genX_pipe_control.c b/src/mesa/drivers/dri/i965/genX_pipe_control.c index 10b8abbb4a0..6cfe9c588e2 100644 --- a/src/mesa/drivers/dri/i965/genX_pipe_control.c +++ b/src/mesa/drivers/dri/i965/genX_pipe_control.c @@ -60,10 +60,10 @@ get_post_sync_flags(enum pipe_control_flags flags) } #define IS_COMPUTE_PIPELINE(brw) \ - (GEN_GEN >= 7 && brw->last_pipeline == BRW_COMPUTE_PIPELINE) + (GFX_VER >= 7 && brw->last_pipeline == BRW_COMPUTE_PIPELINE) -/* Closed interval - GEN_GEN \in [x, y] */ -#define IS_GEN_BETWEEN(x, y) (GEN_GEN >= x && GEN_GEN <= y) +/* Closed interval - GFX_VER \in [x, y] */ +#define IS_GEN_BETWEEN(x, y) (GFX_VER >= x && GFX_VER <= y) #define IS_GENx10_BETWEEN(x, y) \ (GFX_VERx10 >= x && GFX_VERx10 <= y) @@ -94,7 +94,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, * We do these first because we want to look at the original operation, * rather than any workarounds we set. */ - if (GEN_GEN == 6 && (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) { + if (GFX_VER == 6 && (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) { /* Hardware workaround: SNB B-Spec says: * * "[Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush @@ -104,7 +104,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, brw_emit_post_sync_nonzero_flush(brw); } - if (GEN_GEN == 9 && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) { + if (GFX_VER == 9 && (flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) { /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description * lists several workarounds: * @@ -119,7 +119,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, genX(emit_raw_pipe_control)(brw, 0, NULL, 0, 0); } - if (GEN_GEN == 9 && IS_COMPUTE_PIPELINE(brw) && post_sync_flags) { + if (GFX_VER == 9 && IS_COMPUTE_PIPELINE(brw) && post_sync_flags) { /* Project: SKL / Argument: LRI Post Sync Operation [23] * * "PIPECONTROL command with “Command Streamer Stall Enable” must be @@ -162,7 +162,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, PIPE_CONTROL_DEPTH_CACHE_FLUSH))); } - if (GEN_GEN >= 6 && (flags & PIPE_CONTROL_DEPTH_STALL)) { + if (GFX_VER >= 6 && (flags & PIPE_CONTROL_DEPTH_STALL)) { /* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable): * * "This bit must be DISABLED for operations other than writing @@ -199,7 +199,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, PIPE_CONTROL_WRITE_TIMESTAMP))); } - if (GEN_GEN < 11 && (flags & PIPE_CONTROL_STALL_AT_SCOREBOARD)) { + if (GFX_VER < 11 && (flags & PIPE_CONTROL_STALL_AT_SCOREBOARD)) { /* From the PIPE_CONTROL instruction table, bit 1: * * "This bit is ignored if Depth Stall Enable is set. @@ -323,7 +323,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, assert(non_lri_post_sync_flags != 0); } - if (GEN_GEN >= 7 && (flags & PIPE_CONTROL_TLB_INVALIDATE)) { + if (GFX_VER >= 7 && (flags & PIPE_CONTROL_TLB_INVALIDATE)) { /* Project: IVB+ / Argument: TLB inv * * "Requires stall bit ([20] of DW1) set." @@ -340,21 +340,21 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, flags |= PIPE_CONTROL_CS_STALL; } - if (GEN_GEN == 9 && devinfo->gt == 4) { + if (GFX_VER == 9 && devinfo->gt == 4) { /* TODO: The big Skylake GT4 post sync op workaround */ } /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */ if (IS_COMPUTE_PIPELINE(brw)) { - if (GEN_GEN >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { + if (GFX_VER >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { /* Project: SKL+ / Argument: Tex Invalidate * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." */ flags |= PIPE_CONTROL_CS_STALL; } - if (GEN_GEN == 8 && (post_sync_flags || + if (GFX_VER == 8 && (post_sync_flags || (flags & (PIPE_CONTROL_NOTIFY_ENABLE | PIPE_CONTROL_DEPTH_STALL | PIPE_CONTROL_RENDER_TARGET_FLUSH | @@ -425,7 +425,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, * some additional CS stalls above. */ - if (GEN_GEN < 9 && (flags & PIPE_CONTROL_CS_STALL)) { + if (GFX_VER < 9 && (flags & PIPE_CONTROL_CS_STALL)) { /* Project: PRE-SKL, VLV, CHV * * "[All Stepping][All SKUs]: @@ -460,15 +460,15 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, /* Emit --------------------------------------------------------------- */ brw_batch_emit(brw, GENX(PIPE_CONTROL), pc) { - #if GEN_GEN >= 9 + #if GFX_VER >= 9 pc.FlushLLC = 0; #endif - #if GEN_GEN >= 7 + #if GFX_VER >= 7 pc.LRIPostSyncOperation = NoLRIOperation; pc.PipeControlFlushEnable = flags & PIPE_CONTROL_FLUSH_ENABLE; pc.DCFlushEnable = flags & PIPE_CONTROL_DATA_CACHE_FLUSH; #endif - #if GEN_GEN >= 6 + #if GFX_VER >= 6 pc.StoreDataIndex = 0; pc.CommandStreamerStallEnable = flags & PIPE_CONTROL_CS_STALL; pc.GlobalSnapshotCountReset = @@ -492,19 +492,19 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags, pc.InstructionCacheInvalidateEnable = flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE; pc.NotifyEnable = flags & PIPE_CONTROL_NOTIFY_ENABLE; - #if GEN_GEN >= 45 + #if GFX_VER >= 45 pc.IndirectStatePointersDisable = flags & PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE; #endif - #if GEN_GEN >= 6 + #if GFX_VER >= 6 pc.TextureCacheInvalidationEnable = flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; - #elif GEN_GEN == 5 || GFX_VERx10 == 45 + #elif GFX_VER == 5 || GFX_VERx10 == 45 pc.TextureCacheFlushEnable = flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; #endif pc.Address = ggtt_bo(bo, offset); - if (GEN_GEN < 7 && bo) + if (GFX_VER < 7 && bo) pc.DestinationAddressType = DAT_GGTT; pc.ImmediateData = imm; } diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index aec865daac8..fdd0b40ee34 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -61,7 +61,7 @@ #include "main/viewport.h" #include "util/half_float.h" -#if GEN_GEN == 4 +#if GFX_VER == 4 static struct brw_address KSP(struct brw_context *brw, uint32_t offset) { @@ -75,7 +75,7 @@ KSP(UNUSED struct brw_context *brw, uint32_t offset) } #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void emit_lrm(struct brw_context *brw, uint32_t reg, struct brw_address addr) { @@ -86,7 +86,7 @@ emit_lrm(struct brw_context *brw, uint32_t reg, struct brw_address addr) } #endif -#if GEN_GEN == 7 +#if GFX_VER == 7 static void emit_lri(struct brw_context *brw, uint32_t reg, uint32_t imm) { @@ -246,31 +246,31 @@ genX(emit_vertex_buffer_state)(struct brw_context *brw, * the address space. */ .BufferStartingAddress = ro_32_bo(bo, start_offset), -#if GEN_GEN >= 8 +#if GFX_VER >= 8 .BufferSize = end_offset - start_offset, #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 .AddressModifyEnable = true, #endif -#if GEN_GEN < 8 +#if GFX_VER < 8 .BufferAccessType = step_rate ? INSTANCEDATA : VERTEXDATA, .InstanceDataStepRate = step_rate, -#if GEN_GEN >= 5 +#if GFX_VER >= 5 .EndAddress = ro_bo(bo, end_offset - 1), #endif #endif -#if GEN_GEN == 11 +#if GFX_VER == 11 .MOCS = ICL_MOCS_WB, -#elif GEN_GEN == 10 +#elif GFX_VER == 10 .MOCS = CNL_MOCS_WB, -#elif GEN_GEN == 9 +#elif GFX_VER == 9 .MOCS = SKL_MOCS_WB, -#elif GEN_GEN == 8 +#elif GFX_VER == 8 .MOCS = BDW_MOCS_WB, -#elif GEN_GEN == 7 +#elif GFX_VER == 7 .MOCS = GEN7_MOCS_L3, #endif }; @@ -405,7 +405,7 @@ pinned_bo_high_bits(struct brw_bo *bo) static void vf_invalidate_for_vb_48bit_transitions(UNUSED struct brw_context *brw) { -#if GEN_GEN >= 8 && GEN_GEN < 11 +#if GFX_VER >= 8 && GFX_VER < 11 bool need_invalidate = false; for (unsigned i = 0; i < brw->vb.nr_buffers; i++) { @@ -444,7 +444,7 @@ vf_invalidate_for_vb_48bit_transitions(UNUSED struct brw_context *brw) static void vf_invalidate_for_ib_48bit_transition(UNUSED struct brw_context *brw) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 uint16_t high_bits = pinned_bo_high_bits(brw->ib.bo); if (high_bits != brw->ib.last_bo_high_bits) { @@ -463,14 +463,14 @@ genX(emit_vertices)(struct brw_context *brw) brw_prepare_vertices(brw); brw_prepare_shader_draw_parameters(brw); -#if GEN_GEN < 6 +#if GFX_VER < 6 brw_emit_query_begin(brw); #endif const struct brw_vs_prog_data *vs_prog_data = brw_vs_prog_data(brw->vs.base.prog_data); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 struct gl_context *ctx = &brw->ctx; const bool uses_edge_flag = (ctx->Polygon.FrontMode != GL_FILL || ctx->Polygon.BackMode != GL_FILL); @@ -528,7 +528,7 @@ genX(emit_vertices)(struct brw_context *brw) unsigned nr_elements = brw->vb.nr_enabled + needs_sgvs_element + uses_derived_draw_params; -#if GEN_GEN < 8 +#if GFX_VER < 8 /* If any of the formats of vb.enabled needs more that one upload, we need * to add it to nr_elements */ @@ -570,7 +570,7 @@ genX(emit_vertices)(struct brw_context *brw) vf_invalidate_for_vb_48bit_transitions(brw); if (nr_buffers) { - assert(nr_buffers <= (GEN_GEN >= 6 ? 33 : 17)); + assert(nr_buffers <= (GFX_VER >= 6 ? 33 : 17)); dw = brw_batch_emitn(brw, GENX(3DSTATE_VERTEX_BUFFERS), 1 + GENX(VERTEX_BUFFER_STATE_length) * nr_buffers); @@ -614,7 +614,7 @@ genX(emit_vertices)(struct brw_context *brw) /* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, * presumably for VertexID/InstanceID. */ -#if GEN_GEN >= 6 +#if GFX_VER >= 6 assert(nr_elements <= 34); const struct brw_vertex_element *gen6_edgeflag_input = NULL; #else @@ -632,10 +632,10 @@ genX(emit_vertices)(struct brw_context *brw) uint32_t comp1 = VFCOMP_STORE_SRC; uint32_t comp2 = VFCOMP_STORE_SRC; uint32_t comp3 = VFCOMP_STORE_SRC; - const unsigned num_uploads = GEN_GEN < 8 ? + const unsigned num_uploads = GFX_VER < 8 ? uploads_needed(format, input->is_dual_slot) : 1; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* From the BDW PRM, Volume 2d, page 588 (VERTEX_ELEMENT_STATE): * "Any SourceElementFormat of *64*_PASSTHRU cannot be used with an * element which has edge flag enabled." @@ -653,7 +653,7 @@ genX(emit_vertices)(struct brw_context *brw) * of in the VUE. We have to upload it sideband as the last vertex * element according to the B-Spec. */ -#if GEN_GEN >= 6 +#if GFX_VER >= 6 if (input == &brw->vb.inputs[VERT_ATTRIB_EDGEFLAG]) { gen6_edgeflag_input = input; continue; @@ -661,14 +661,14 @@ genX(emit_vertices)(struct brw_context *brw) #endif for (unsigned c = 0; c < num_uploads; c++) { - const uint32_t upload_format = GEN_GEN >= 8 ? format : + const uint32_t upload_format = GFX_VER >= 8 ? format : downsize_format_if_needed(format, c); /* If we need more that one upload, the offset stride would be 128 * bits (16 bytes), as for previous uploads we are using the full * entry. */ const unsigned offset = input->offset + c * 16; - const int size = (GEN_GEN < 8 && is_passthru_format(format)) ? + const int size = (GFX_VER < 8 && is_passthru_format(format)) ? upload_format_size(upload_format) : glformat->Size; switch (size) { @@ -676,7 +676,7 @@ genX(emit_vertices)(struct brw_context *brw) case 1: comp1 = VFCOMP_STORE_0; /* fallthrough */ case 2: comp2 = VFCOMP_STORE_0; /* fallthrough */ case 3: - if (GEN_GEN >= 8 && glformat->Doubles) { + if (GFX_VER >= 8 && glformat->Doubles) { comp3 = VFCOMP_STORE_0; } else if (glformat->Integer) { comp3 = VFCOMP_STORE_1_INT; @@ -687,7 +687,7 @@ genX(emit_vertices)(struct brw_context *brw) break; } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* From the BDW PRM, Volume 2d, page 586 (VERTEX_ELEMENT_STATE): * * "When SourceElementFormat is set to one of the *64*_PASSTHRU @@ -721,7 +721,7 @@ genX(emit_vertices)(struct brw_context *brw) .Component1Control = comp1, .Component2Control = comp2, .Component3Control = comp3, -#if GEN_GEN < 5 +#if GFX_VER < 5 .DestinationElementOffset = i * 4, #endif }; @@ -738,12 +738,12 @@ genX(emit_vertices)(struct brw_context *brw) .Component1Control = VFCOMP_STORE_0, .Component2Control = VFCOMP_STORE_0, .Component3Control = VFCOMP_STORE_0, -#if GEN_GEN < 5 +#if GFX_VER < 5 .DestinationElementOffset = i * 4, #endif }; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 if (uses_draw_params) { elem_state.VertexBufferIndex = brw->vb.nr_buffers; elem_state.SourceElementFormat = ISL_FORMAT_R32G32_UINT; @@ -778,7 +778,7 @@ genX(emit_vertices)(struct brw_context *brw) .Component1Control = VFCOMP_STORE_SRC, .Component2Control = VFCOMP_STORE_0, .Component3Control = VFCOMP_STORE_0, -#if GEN_GEN < 5 +#if GFX_VER < 5 .DestinationElementOffset = i * 4, #endif }; @@ -787,7 +787,7 @@ genX(emit_vertices)(struct brw_context *brw) dw += GENX(VERTEX_ELEMENT_STATE_length); } -#if GEN_GEN >= 6 +#if GFX_VER >= 6 if (gen6_edgeflag_input) { const struct gl_vertex_format *glformat = gen6_edgeflag_input->glformat; const uint32_t format = brw_get_vertex_surface_type(brw, glformat); @@ -809,7 +809,7 @@ genX(emit_vertices)(struct brw_context *brw) } #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 for (unsigned i = 0, j = 0; i < brw->vb.nr_enabled; i++) { const struct brw_vertex_element *input = brw->vb.enabled[i]; const struct brw_vertex_buffer *buffer = &brw->vb.buffers[input->buffer]; @@ -878,8 +878,8 @@ genX(emit_index_buffer)(struct brw_context *brw) * the address space. */ ib.BufferStartingAddress = ro_32_bo(brw->ib.bo, 0); -#if GEN_GEN >= 8 - ib.MOCS = GEN_GEN >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; +#if GFX_VER >= 8 + ib.MOCS = GFX_VER >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; ib.BufferSize = brw->ib.size; #else ib.BufferEndingAddress = ro_bo(brw->ib.bo, brw->ib.size - 1); @@ -934,7 +934,7 @@ const struct brw_tracked_state genX(vf_statistics) = { .emit = genX(upload_vf_statistics), }; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 /** * Determine the appropriate attribute override value to store into the * 3DSTATE_SF structure for a given fragment shader attribute. The attribute @@ -1162,9 +1162,9 @@ genX(calculate_attr_overrides)(const struct brw_context *brw, /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 typedef struct GENX(3DSTATE_WM_DEPTH_STENCIL) DEPTH_STENCIL_GENXML; -#elif GEN_GEN >= 6 +#elif GFX_VER >= 6 typedef struct GENX(DEPTH_STENCIL_STATE) DEPTH_STENCIL_GENXML; #else typedef struct GENX(COLOR_CALC_STATE) DEPTH_STENCIL_GENXML; @@ -1223,18 +1223,18 @@ set_depth_stencil_bits(struct brw_context *brw, DEPTH_STENCIL_GENXML *ds) brw_translate_stencil_op(stencil->ZFailFunc[b]); } -#if GEN_GEN <= 5 || GEN_GEN >= 9 +#if GFX_VER <= 5 || GFX_VER >= 9 ds->StencilReferenceValue = _mesa_get_stencil_ref(ctx, 0); ds->BackfaceStencilReferenceValue = _mesa_get_stencil_ref(ctx, b); #endif } } -#if GEN_GEN >= 6 +#if GFX_VER >= 6 static void genX(upload_depth_stencil_state)(struct brw_context *brw) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 brw_batch_emit(brw, GENX(3DSTATE_WM_DEPTH_STENCIL), wmds) { set_depth_stencil_bits(brw, &wmds); } @@ -1245,7 +1245,7 @@ genX(upload_depth_stencil_state)(struct brw_context *brw) } /* Now upload a pointer to the indirect state */ -#if GEN_GEN == 6 +#if GFX_VER == 6 brw_batch_emit(brw, GENX(3DSTATE_CC_STATE_POINTERS), ptr) { ptr.PointertoDEPTH_STENCIL_STATE = ds_offset; ptr.DEPTH_STENCIL_STATEChange = true; @@ -1264,7 +1264,7 @@ static const struct brw_tracked_state genX(depth_stencil_state) = { _NEW_DEPTH | _NEW_STENCIL, .brw = BRW_NEW_BLORP | - (GEN_GEN >= 8 ? BRW_NEW_CONTEXT + (GFX_VER >= 8 ? BRW_NEW_CONTEXT : BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS), }, @@ -1274,7 +1274,7 @@ static const struct brw_tracked_state genX(depth_stencil_state) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN <= 5 +#if GFX_VER <= 5 static void genX(upload_clip_state)(struct brw_context *brw) @@ -1309,7 +1309,7 @@ genX(upload_clip_state)(struct brw_context *brw) /* Although up to 16 concurrent Clip threads are allowed on Ironlake, * only 2 threads can output VUEs at a time. */ - clip.MaximumNumberofThreads = (GEN_GEN == 5 ? 16 : 2) - 1; + clip.MaximumNumberofThreads = (GFX_VER == 5 ? 16 : 2) - 1; } else { assert(brw->urb.nr_clip_entries >= 5); clip.MaximumNumberofThreads = 1 - 1; @@ -1332,7 +1332,7 @@ genX(upload_clip_state)(struct brw_context *brw) ctx->Transform.DepthClampFar); /* _NEW_TRANSFORM */ - if (GEN_GEN == 5 || GFX_VERx10 == 45) { + if (GFX_VER == 5 || GFX_VERx10 == 45) { clip.UserClipDistanceClipTestEnableBitmask = ctx->Transform.ClipPlanesEnabled; } else { @@ -1393,11 +1393,11 @@ genX(upload_clip_state)(struct brw_context *brw) BRW_BARYCENTRIC_NONPERSPECTIVE_BITS) clip.NonPerspectiveBarycentricEnable = true; -#if GEN_GEN >= 7 +#if GFX_VER >= 7 clip.EarlyCullEnable = true; #endif -#if GEN_GEN == 7 +#if GFX_VER == 7 clip.FrontWinding = brw->polygon_front_bit != fb->FlipY; if (ctx->Polygon.CullFlag) { @@ -1419,7 +1419,7 @@ genX(upload_clip_state)(struct brw_context *brw) } #endif -#if GEN_GEN < 8 +#if GFX_VER < 8 clip.UserClipDistanceCullTestEnableBitmask = brw_vue_prog_data(brw->vs.base.prog_data)->cull_distance_mask; @@ -1442,7 +1442,7 @@ genX(upload_clip_state)(struct brw_context *brw) clip.UserClipDistanceClipTestEnableBitmask = ctx->Transform.ClipPlanesEnabled; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 clip.ForceUserClipDistanceClipTestEnableBitmask = true; #endif @@ -1458,7 +1458,7 @@ genX(upload_clip_state)(struct brw_context *brw) if (ctx->RasterDiscard) { clip.ClipMode = CLIPMODE_REJECT_ALL; -#if GEN_GEN == 6 +#if GFX_VER == 6 perf_debug("Rasterizer discard is currently implemented via the " "clipper; having the GS not write primitives would " "likely be faster.\n"); @@ -1512,14 +1512,14 @@ genX(upload_sf)(struct brw_context *brw) struct gl_context *ctx = &brw->ctx; float point_size; -#if GEN_GEN <= 7 +#if GFX_VER <= 7 /* _NEW_BUFFERS */ bool flip_y = ctx->DrawBuffer->FlipY; UNUSED const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1; #endif -#if GEN_GEN < 6 +#if GFX_VER < 6 const struct brw_sf_prog_data *sf_prog_data = brw->sf.prog_data; ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; @@ -1547,7 +1547,7 @@ genX(upload_sf)(struct brw_context *brw) /* sf.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; */ sf.MaximumNumberofThreads = - MIN2(GEN_GEN == 5 ? 48 : 24, brw->urb.nr_sf_entries) - 1; + MIN2(GFX_VER == 5 ? 48 : 24, brw->urb.nr_sf_entries) - 1; sf.SpritePointEnable = ctx->Point.PointSprite; @@ -1559,15 +1559,15 @@ genX(upload_sf)(struct brw_context *brw) #endif sf.ViewportTransformEnable = true; -#if GEN_GEN == 7 +#if GFX_VER == 7 /* _NEW_BUFFERS */ sf.DepthBufferSurfaceFormat = brw_depthbuffer_format(brw); #endif -#if GEN_GEN <= 7 +#if GFX_VER <= 7 /* _NEW_POLYGON */ sf.FrontWinding = brw->polygon_front_bit != flip_y; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 sf.GlobalDepthOffsetEnableSolid = ctx->Polygon.OffsetFill; sf.GlobalDepthOffsetEnableWireframe = ctx->Polygon.OffsetLine; sf.GlobalDepthOffsetEnablePoint = ctx->Polygon.OffsetPoint; @@ -1635,7 +1635,7 @@ genX(upload_sf)(struct brw_context *brw) #endif /* _NEW_LINE */ -#if GEN_GEN == 8 +#if GFX_VER == 8 const struct gen_device_info *devinfo = &brw->screen->devinfo; if (devinfo->is_cherryview) @@ -1648,7 +1648,7 @@ genX(upload_sf)(struct brw_context *brw) if (ctx->Line.SmoothFlag) { sf.LineEndCapAntialiasingRegionWidth = _10pixels; -#if GEN_GEN <= 7 +#if GFX_VER <= 7 sf.AntialiasingEnable = true; #endif } @@ -1662,14 +1662,14 @@ genX(upload_sf)(struct brw_context *brw) if (use_state_point_size(brw)) sf.PointWidthSource = State; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* _NEW_POINT | _NEW_MULTISAMPLE */ if ((ctx->Point.SmoothFlag || _mesa_is_multisample_enabled(ctx)) && !ctx->Point.PointSprite) sf.SmoothPointEnable = true; #endif -#if GEN_GEN == 10 +#if GFX_VER == 10 /* _NEW_BUFFERS * Smooth Point Enable bit MUST not be set when NUM_MULTISAMPLES > 1. */ @@ -1692,7 +1692,7 @@ genX(upload_sf)(struct brw_context *brw) sf.TriangleFanProvokingVertexSelect = 1; } -#if GEN_GEN == 6 +#if GFX_VER == 6 /* BRW_NEW_FS_PROG_DATA */ const struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(brw->wm.base.prog_data); @@ -1733,24 +1733,24 @@ static const struct brw_tracked_state genX(sf_state) = { _NEW_LINE | _NEW_POINT | _NEW_PROGRAM | - (GEN_GEN >= 6 ? _NEW_MULTISAMPLE : 0) | - (GEN_GEN <= 7 ? _NEW_BUFFERS | _NEW_POLYGON : 0) | - (GEN_GEN == 10 ? _NEW_BUFFERS : 0), + (GFX_VER >= 6 ? _NEW_MULTISAMPLE : 0) | + (GFX_VER <= 7 ? _NEW_BUFFERS | _NEW_POLYGON : 0) | + (GFX_VER == 10 ? _NEW_BUFFERS : 0), .brw = BRW_NEW_BLORP | BRW_NEW_VUE_MAP_GEOM_OUT | - (GEN_GEN <= 5 ? BRW_NEW_BATCH | + (GFX_VER <= 5 ? BRW_NEW_BATCH | BRW_NEW_PROGRAM_CACHE | BRW_NEW_SF_PROG_DATA | BRW_NEW_SF_VP | BRW_NEW_URB_FENCE : 0) | - (GEN_GEN >= 6 ? BRW_NEW_CONTEXT : 0) | - (GEN_GEN >= 6 && GEN_GEN <= 7 ? + (GFX_VER >= 6 ? BRW_NEW_CONTEXT : 0) | + (GFX_VER >= 6 && GFX_VER <= 7 ? BRW_NEW_GS_PROG_DATA | BRW_NEW_PRIMITIVE | BRW_NEW_TES_PROG_DATA : 0) | - (GEN_GEN == 6 ? BRW_NEW_FS_PROG_DATA | + (GFX_VER == 6 ? BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM : 0), }, @@ -1797,7 +1797,7 @@ genX(upload_wm)(struct brw_context *brw) UNUSED struct brw_stage_state *stage_state = &brw->wm.base; UNUSED const struct gen_device_info *devinfo = &brw->screen->devinfo; -#if GEN_GEN == 6 +#if GFX_VER == 6 /* We can't fold this into gen6_upload_wm_push_constants(), because * according to the SNB PRM, vol 2 part 1 section 7.2.2 * (3DSTATE_CONSTANT_PS [DevSNB]): @@ -1816,20 +1816,20 @@ genX(upload_wm)(struct brw_context *brw) } #endif -#if GEN_GEN >= 6 +#if GFX_VER >= 6 brw_batch_emit(brw, GENX(3DSTATE_WM), wm) { #else ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; brw_state_emit(brw, GENX(WM_STATE), 64, &stage_state->state_offset, wm) { #endif -#if GEN_GEN <= 6 +#if GFX_VER <= 6 wm._8PixelDispatchEnable = wm_prog_data->dispatch_8; wm._16PixelDispatchEnable = wm_prog_data->dispatch_16; wm._32PixelDispatchEnable = wm_prog_data->dispatch_32; #endif -#if GEN_GEN == 4 +#if GFX_VER == 4 /* On gen4, we only have one shader kernel */ if (brw_wm_state_has_ksp(wm, 0)) { assert(brw_wm_prog_data_prog_offset(wm_prog_data, wm, 0) == 0); @@ -1838,7 +1838,7 @@ genX(upload_wm)(struct brw_context *brw) wm.DispatchGRFStartRegisterForConstantSetupData0 = brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 0); } -#elif GEN_GEN == 5 +#elif GFX_VER == 5 /* On gen5, we have multiple shader kernels but only one GRF start * register for all kernels */ @@ -1865,7 +1865,7 @@ genX(upload_wm)(struct brw_context *brw) assert(wm_prog_data->base.dispatch_grf_start_reg == brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 2)); } -#elif GEN_GEN == 6 +#elif GFX_VER == 6 /* On gen6, we have multiple shader kernels and we no longer specify a * register count for each one. */ @@ -1884,7 +1884,7 @@ genX(upload_wm)(struct brw_context *brw) brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, wm, 2); #endif -#if GEN_GEN <= 5 +#if GFX_VER <= 5 wm.ConstantURBEntryReadLength = wm_prog_data->base.curb_read_length; /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */ wm.ConstantURBEntryReadOffset = brw->curbe.wm_start * 2; @@ -1893,7 +1893,7 @@ genX(upload_wm)(struct brw_context *brw) wm.EarlyDepthTestEnable = true; #endif -#if GEN_GEN >= 6 +#if GFX_VER >= 6 wm.LineAntialiasingRegionWidth = _10pixels; wm.LineEndCapAntialiasingRegionWidth = _05pixels; @@ -1926,20 +1926,20 @@ genX(upload_wm)(struct brw_context *brw) #endif /* BRW_NEW_STATS_WM */ - wm.StatisticsEnable = GEN_GEN >= 6 || brw->stats_wm; + wm.StatisticsEnable = GFX_VER >= 6 || brw->stats_wm; -#if GEN_GEN < 7 +#if GFX_VER < 7 if (wm_prog_data->base.use_alt_mode) wm.FloatingPointMode = FLOATING_POINT_MODE_Alternate; - wm.SamplerCount = GEN_GEN == 5 ? + wm.SamplerCount = GFX_VER == 5 ? 0 : DIV_ROUND_UP(stage_state->sampler_count, 4); wm.BindingTableEntryCount = wm_prog_data->base.binding_table.size_bytes / 4; wm.MaximumNumberofThreads = devinfo->max_wm_threads - 1; -#if GEN_GEN == 6 +#if GFX_VER == 6 wm.DualSourceBlendEnable = wm_prog_data->dual_src_blend && (ctx->Color.BlendEnabled & 1) && ctx->Color._BlendUsesDualSrc & 0x1; @@ -1979,9 +1979,9 @@ genX(upload_wm)(struct brw_context *brw) /* _NEW_POLYGON */ wm.PolygonStippleEnable = ctx->Polygon.StippleFlag; -#if GEN_GEN < 8 +#if GFX_VER < 8 -#if GEN_GEN >= 6 +#if GFX_VER >= 6 wm.PixelShaderUsesSourceW = wm_prog_data->uses_src_w; /* _NEW_BUFFERS */ @@ -2007,18 +2007,18 @@ genX(upload_wm)(struct brw_context *brw) if (wm_prog_data->uses_kill || _mesa_is_alpha_test_enabled(ctx) || _mesa_is_alpha_to_coverage_enabled(ctx) || - (GEN_GEN >= 6 && wm_prog_data->uses_omask)) { + (GFX_VER >= 6 && wm_prog_data->uses_omask)) { wm.PixelShaderKillsPixel = true; } /* _NEW_BUFFERS | _NEW_COLOR */ if (brw_color_buffer_write_enabled(brw) || writes_depth || wm.PixelShaderKillsPixel || - (GEN_GEN >= 6 && wm_prog_data->has_side_effects)) { + (GFX_VER >= 6 && wm_prog_data->has_side_effects)) { wm.ThreadDispatchEnable = true; } -#if GEN_GEN >= 7 +#if GFX_VER >= 7 wm.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode; wm.PixelShaderUsesInputCoverageMask = wm_prog_data->uses_sample_mask; #endif @@ -2039,7 +2039,7 @@ genX(upload_wm)(struct brw_context *brw) #endif #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 /* BRW_NEW_FS_PROG_DATA */ if (wm_prog_data->early_fragment_tests) wm.EarlyDepthStencilControl = EDSC_PREPS; @@ -2048,7 +2048,7 @@ genX(upload_wm)(struct brw_context *brw) #endif } -#if GEN_GEN <= 5 +#if GFX_VER <= 5 if (brw->wm.offset_clamp != ctx->Polygon.OffsetClamp) { brw_batch_emit(brw, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP), clamp) { clamp.GlobalDepthOffsetClamp = ctx->Polygon.OffsetClamp; @@ -2063,21 +2063,21 @@ static const struct brw_tracked_state genX(wm_state) = { .dirty = { .mesa = _NEW_LINE | _NEW_POLYGON | - (GEN_GEN < 8 ? _NEW_BUFFERS | + (GFX_VER < 8 ? _NEW_BUFFERS | _NEW_COLOR : 0) | - (GEN_GEN == 6 ? _NEW_PROGRAM_CONSTANTS : 0) | - (GEN_GEN < 6 ? _NEW_POLYGONSTIPPLE : 0) | - (GEN_GEN < 8 && GEN_GEN >= 6 ? _NEW_MULTISAMPLE : 0), + (GFX_VER == 6 ? _NEW_PROGRAM_CONSTANTS : 0) | + (GFX_VER < 6 ? _NEW_POLYGONSTIPPLE : 0) | + (GFX_VER < 8 && GFX_VER >= 6 ? _NEW_MULTISAMPLE : 0), .brw = BRW_NEW_BLORP | BRW_NEW_FS_PROG_DATA | - (GEN_GEN < 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION | + (GFX_VER < 6 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION | BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_PROGRAM_CACHE | BRW_NEW_SAMPLER_STATE_TABLE | BRW_NEW_STATS_WM : 0) | - (GEN_GEN < 7 ? BRW_NEW_BATCH : BRW_NEW_CONTEXT), + (GFX_VER < 7 ? BRW_NEW_BATCH : BRW_NEW_CONTEXT), }, .emit = genX(upload_wm), }; @@ -2096,7 +2096,7 @@ static const struct brw_tracked_state genX(wm_state) = { pkt.KernelStartPointer = KSP(brw, stage_state->prog_offset); \ /* WA_1606682166 */ \ pkt.SamplerCount = \ - GEN_GEN == 11 ? \ + GFX_VER == 11 ? \ 0 : \ DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); \ pkt.BindingTableEntryCount = \ @@ -2131,10 +2131,10 @@ genX(upload_vs_state)(struct brw_context *brw) assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 || vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT); - assert(GEN_GEN < 11 || + assert(GFX_VER < 11 || vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8); -#if GEN_GEN == 6 +#if GFX_VER == 6 /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State, * 3DSTATE_VS, Dword 5.0 "VS Function Enable": * @@ -2155,10 +2155,10 @@ genX(upload_vs_state)(struct brw_context *brw) } #endif - if (GEN_GEN == 7 && devinfo->is_ivybridge) + if (GFX_VER == 7 && devinfo->is_ivybridge) gen7_emit_vs_workaround_flush(brw); -#if GEN_GEN >= 6 +#if GFX_VER >= 6 brw_batch_emit(brw, GENX(3DSTATE_VS), vs) { #else ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; @@ -2168,12 +2168,12 @@ genX(upload_vs_state)(struct brw_context *brw) vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1; -#if GEN_GEN < 6 +#if GFX_VER < 6 vs.GRFRegisterCount = DIV_ROUND_UP(vue_prog_data->total_grf, 16) - 1; vs.ConstantURBEntryReadLength = stage_prog_data->curb_read_length; vs.ConstantURBEntryReadOffset = brw->curbe.vs_start * 2; - vs.NumberofURBEntries = brw->urb.nr_vs_entries >> (GEN_GEN == 5 ? 2 : 0); + vs.NumberofURBEntries = brw->urb.nr_vs_entries >> (GFX_VER == 5 ? 2 : 0); vs.URBEntryAllocationSize = brw->urb.vsize - 1; vs.MaximumNumberofThreads = @@ -2184,7 +2184,7 @@ genX(upload_vs_state)(struct brw_context *brw) ro_bo(brw->batch.state.bo, stage_state->sampler_offset); #endif -#if GEN_GEN == 5 +#if GFX_VER == 5 /* Force single program flow on Ironlake. We cannot reliably get * all applications working without it. See: * https://bugs.freedesktop.org/show_bug.cgi?id=29172 @@ -2196,7 +2196,7 @@ genX(upload_vs_state)(struct brw_context *brw) vs.SamplerCount = 0; /* hardware requirement */ #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 vs.SIMD8DispatchEnable = vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8; @@ -2205,7 +2205,7 @@ genX(upload_vs_state)(struct brw_context *brw) #endif } -#if GEN_GEN == 6 +#if GFX_VER == 6 /* Based on my reading of the simulator, the VS constants don't get * pulled into the VS FF unit until an appropriate pipeline flush * happens, and instead the 3DSTATE_CONSTANT_VS packet just adds @@ -2232,13 +2232,13 @@ genX(upload_vs_state)(struct brw_context *brw) static const struct brw_tracked_state genX(vs_state) = { .dirty = { - .mesa = (GEN_GEN == 6 ? (_NEW_PROGRAM_CONSTANTS | _NEW_TRANSFORM) : 0), + .mesa = (GFX_VER == 6 ? (_NEW_PROGRAM_CONSTANTS | _NEW_TRANSFORM) : 0), .brw = BRW_NEW_BATCH | BRW_NEW_BLORP | BRW_NEW_CONTEXT | BRW_NEW_VS_PROG_DATA | - (GEN_GEN == 6 ? BRW_NEW_VERTEX_PROGRAM : 0) | - (GEN_GEN <= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION | + (GFX_VER == 6 ? BRW_NEW_VERTEX_PROGRAM : 0) | + (GFX_VER <= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION | BRW_NEW_PROGRAM_CACHE | BRW_NEW_SAMPLER_STATE_TABLE | BRW_NEW_URB_FENCE @@ -2283,11 +2283,11 @@ genX(upload_cc_viewport)(struct brw_context *brw) cc_map += GENX(CC_VIEWPORT_length); } -#if GEN_GEN >= 7 +#if GFX_VER >= 7 brw_batch_emit(brw, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) { ptr.CCViewportPointer = cc_vp_offset; } -#elif GEN_GEN == 6 +#elif GFX_VER == 6 brw_batch_emit(brw, GENX(3DSTATE_VIEWPORT_STATE_POINTERS), vp) { vp.CCViewportStateChange = 1; vp.PointertoCC_VIEWPORT = cc_vp_offset; @@ -2350,7 +2350,7 @@ set_scissor_bits(const struct gl_context *ctx, int i, } } -#if GEN_GEN >= 6 +#if GFX_VER >= 6 static void genX(upload_scissor_state)(struct brw_context *brw) { @@ -2424,7 +2424,7 @@ genX(upload_sf_clip_viewport)(struct brw_context *brw) const uint32_t fb_width = (float)_mesa_geometric_width(ctx->DrawBuffer); const uint32_t fb_height = (float)_mesa_geometric_height(ctx->DrawBuffer); -#if GEN_GEN >= 7 +#if GFX_VER >= 7 #define clv sfv struct GENX(SF_CLIP_VIEWPORT) sfv; uint32_t sf_clip_vp_offset; @@ -2476,10 +2476,10 @@ genX(upload_sf_clip_viewport)(struct brw_context *brw) clv.YMinClipGuardband = gb_ymin; clv.YMaxClipGuardband = gb_ymax; -#if GEN_GEN < 6 +#if GFX_VER < 6 set_scissor_bits(ctx, i, flip_y, fb_width, fb_height, &sfv.ScissorRectangle); -#elif GEN_GEN >= 8 +#elif GFX_VER >= 8 /* _NEW_VIEWPORT | _NEW_BUFFERS: Screen Space Viewport * The hardware will take the intersection of the drawing rectangle, * scissor rectangle, and the viewport extents. However, emitting @@ -2507,7 +2507,7 @@ genX(upload_sf_clip_viewport)(struct brw_context *brw) } #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 GENX(SF_CLIP_VIEWPORT_pack)(NULL, sf_clip_map, &sfv); sf_clip_map += GENX(SF_CLIP_VIEWPORT_length); #else @@ -2518,11 +2518,11 @@ genX(upload_sf_clip_viewport)(struct brw_context *brw) #endif } -#if GEN_GEN >= 7 +#if GFX_VER >= 7 brw_batch_emit(brw, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) { ptr.SFClipViewportPointer = sf_clip_vp_offset; } -#elif GEN_GEN == 6 +#elif GFX_VER == 6 brw_batch_emit(brw, GENX(3DSTATE_VIEWPORT_STATE_POINTERS), vp) { vp.SFViewportStateChange = 1; vp.CLIPViewportStateChange = 1; @@ -2540,7 +2540,7 @@ static const struct brw_tracked_state genX(sf_clip_viewport) = { .dirty = { .mesa = _NEW_BUFFERS | _NEW_VIEWPORT | - (GEN_GEN <= 5 ? _NEW_SCISSOR : 0), + (GFX_VER <= 5 ? _NEW_SCISSOR : 0), .brw = BRW_NEW_BATCH | BRW_NEW_BLORP | BRW_NEW_VIEWPORT_COUNT, @@ -2558,18 +2558,18 @@ genX(upload_gs_state)(struct brw_context *brw) const struct brw_stage_state *stage_state = &brw->gs.base; const struct gl_program *gs_prog = brw->programs[MESA_SHADER_GEOMETRY]; /* BRW_NEW_GEOMETRY_PROGRAM */ - bool active = GEN_GEN >= 6 && gs_prog; + bool active = GFX_VER >= 6 && gs_prog; /* BRW_NEW_GS_PROG_DATA */ struct brw_stage_prog_data *stage_prog_data = stage_state->prog_data; UNUSED const struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(stage_prog_data); -#if GEN_GEN >= 7 +#if GFX_VER >= 7 const struct brw_gs_prog_data *gs_prog_data = brw_gs_prog_data(stage_prog_data); #endif -#if GEN_GEN == 6 +#if GFX_VER == 6 brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_GS), cgs) { if (active && stage_state->push_const_size != 0) { cgs.Buffer0Valid = true; @@ -2596,18 +2596,18 @@ genX(upload_gs_state)(struct brw_context *brw) gen7_emit_cs_stall_flush(brw); #endif -#if GEN_GEN >= 6 +#if GFX_VER >= 6 brw_batch_emit(brw, GENX(3DSTATE_GS), gs) { #else ctx->NewDriverState |= BRW_NEW_GEN4_UNIT_STATE; brw_state_emit(brw, GENX(GS_STATE), 32, &brw->ff_gs.state_offset, gs) { #endif -#if GEN_GEN >= 6 +#if GFX_VER >= 6 if (active) { INIT_THREAD_DISPATCH_FIELDS(gs, Vertex); -#if GEN_GEN >= 7 +#if GFX_VER >= 7 gs.OutputVertexSize = gs_prog_data->output_vertex_size_hwords * 2 - 1; gs.OutputTopology = gs_prog_data->output_topology; gs.ControlDataHeaderSize = @@ -2649,10 +2649,10 @@ genX(upload_gs_state)(struct brw_context *brw) */ gs.ReorderMode = TRAILING; gs.MaximumNumberofThreads = - GEN_GEN == 8 ? (devinfo->max_gs_threads / 2 - 1) + GFX_VER == 8 ? (devinfo->max_gs_threads / 2 - 1) : (devinfo->max_gs_threads - 1); -#if GEN_GEN < 7 +#if GFX_VER < 7 gs.SOStatisticsEnable = true; if (gs_prog->info.has_transform_feedback_varyings) gs.SVBIPayloadEnable = _mesa_is_xfb_active_and_unpaused(ctx); @@ -2667,7 +2667,7 @@ genX(upload_gs_state)(struct brw_context *brw) gs.VectorMaskEnable = true; #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 gs.ExpectedVertexCount = gs_prog_data->vertices_in; if (gs_prog_data->static_vertex_count != -1) { @@ -2690,7 +2690,7 @@ genX(upload_gs_state)(struct brw_context *brw) } #endif -#if GEN_GEN <= 6 +#if GFX_VER <= 6 if (!active && brw->ff_gs.prog_active) { /* In gen6, transform feedback for the VS stage is done with an * ad-hoc GS program. This function provides the needed 3DSTATE_GS @@ -2698,10 +2698,10 @@ genX(upload_gs_state)(struct brw_context *brw) */ gs.KernelStartPointer = KSP(brw, brw->ff_gs.prog_offset); gs.SingleProgramFlow = true; - gs.DispatchGRFStartRegisterForURBData = GEN_GEN == 6 ? 2 : 1; + gs.DispatchGRFStartRegisterForURBData = GFX_VER == 6 ? 2 : 1; gs.VertexURBEntryReadLength = brw->ff_gs.prog_data->urb_read_length; -#if GEN_GEN <= 5 +#if GFX_VER <= 5 gs.GRFRegisterCount = DIV_ROUND_UP(brw->ff_gs.prog_data->total_grf, 16) - 1; /* BRW_NEW_URB_FENCE */ @@ -2722,45 +2722,45 @@ genX(upload_gs_state)(struct brw_context *brw) } #endif if (!active && !brw->ff_gs.prog_active) { -#if GEN_GEN < 8 +#if GFX_VER < 8 gs.DispatchGRFStartRegisterForURBData = 1; -#if GEN_GEN >= 7 +#if GFX_VER >= 7 gs.IncludeVertexHandles = true; #endif #endif } -#if GEN_GEN >= 6 +#if GFX_VER >= 6 gs.StatisticsEnable = true; #endif -#if GEN_GEN == 5 || GEN_GEN == 6 +#if GFX_VER == 5 || GFX_VER == 6 gs.RenderingEnabled = true; #endif -#if GEN_GEN <= 5 +#if GFX_VER <= 5 gs.MaximumVPIndex = brw->clip.viewport_count - 1; #endif } -#if GEN_GEN == 6 +#if GFX_VER == 6 brw->gs.enabled = active; #endif } static const struct brw_tracked_state genX(gs_state) = { .dirty = { - .mesa = (GEN_GEN == 6 ? _NEW_PROGRAM_CONSTANTS : 0), + .mesa = (GFX_VER == 6 ? _NEW_PROGRAM_CONSTANTS : 0), .brw = BRW_NEW_BATCH | BRW_NEW_BLORP | - (GEN_GEN <= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION | + (GFX_VER <= 5 ? BRW_NEW_PUSH_CONSTANT_ALLOCATION | BRW_NEW_PROGRAM_CACHE | BRW_NEW_URB_FENCE | BRW_NEW_VIEWPORT_COUNT : 0) | - (GEN_GEN >= 6 ? BRW_NEW_CONTEXT | + (GFX_VER >= 6 ? BRW_NEW_CONTEXT | BRW_NEW_GEOMETRY_PROGRAM | BRW_NEW_GS_PROG_DATA : 0) | - (GEN_GEN < 7 ? BRW_NEW_FF_GS_PROG_DATA : 0), + (GFX_VER < 7 ? BRW_NEW_FF_GS_PROG_DATA : 0), }, .emit = genX(upload_gs_state), }; @@ -2806,7 +2806,7 @@ brw_fix_xRGB_alpha(GLenum function) return function; } -#if GEN_GEN >= 6 +#if GFX_VER >= 6 typedef struct GENX(BLEND_STATE_ENTRY) BLEND_ENTRY_GENXML; #else typedef struct GENX(COLOR_CALC_STATE) BLEND_ENTRY_GENXML; @@ -2831,7 +2831,7 @@ set_blend_entry_bits(struct brw_context *brw, BLEND_ENTRY_GENXML *entry, int i, */ const bool integer = ctx->DrawBuffer->_IntegerBuffers & (0x1 << i); - const unsigned blend_enabled = GEN_GEN >= 6 ? + const unsigned blend_enabled = GFX_VER >= 6 ? ctx->Color.BlendEnabled & (1 << i) : ctx->Color.BlendEnabled; /* _NEW_COLOR */ @@ -2844,13 +2844,13 @@ set_blend_entry_bits(struct brw_context *brw, BLEND_ENTRY_GENXML *entry, int i, "renderbuffer\n", _mesa_enum_to_string(ctx->Color.LogicOp), _mesa_enum_to_string(rb_type)); - if (GEN_GEN >= 8 || rb_type == GL_UNSIGNED_NORMALIZED) { + if (GFX_VER >= 8 || rb_type == GL_UNSIGNED_NORMALIZED) { entry->LogicOpEnable = true; entry->LogicOpFunction = ctx->Color._LogicOp; } } else if (blend_enabled && ctx->Color._AdvancedBlendMode == BLEND_NONE - && (GEN_GEN <= 5 || !integer)) { + && (GFX_VER <= 5 || !integer)) { GLenum eqRGB = ctx->Color.Blend[i].EquationRGB; GLenum eqA = ctx->Color.Blend[i].EquationA; GLenum srcRGB = ctx->Color.Blend[i].SrcRGB; @@ -2885,7 +2885,7 @@ set_blend_entry_bits(struct brw_context *brw, BLEND_ENTRY_GENXML *entry, int i, * We override SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO, * and leave it enabled anyway. */ - if (GEN_GEN >= 6 && ctx->Color._BlendUsesDualSrc & (1 << i) && alpha_to_one) { + if (GFX_VER >= 6 && ctx->Color._BlendUsesDualSrc & (1 << i) && alpha_to_one) { srcRGB = fix_dual_blend_alpha_to_one(srcRGB); srcA = fix_dual_blend_alpha_to_one(srcA); dstRGB = fix_dual_blend_alpha_to_one(dstRGB); @@ -2926,7 +2926,7 @@ set_blend_entry_bits(struct brw_context *brw, BLEND_ENTRY_GENXML *entry, int i, return independent_alpha_blend; } -#if GEN_GEN >= 6 +#if GFX_VER >= 6 static void genX(upload_blend_state)(struct brw_context *brw) { @@ -2944,14 +2944,14 @@ genX(upload_blend_state)(struct brw_context *brw) nr_draw_buffers = 1; size = GENX(BLEND_STATE_ENTRY_length) * 4 * nr_draw_buffers; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 size += GENX(BLEND_STATE_length) * 4; #endif uint32_t *blend_map; blend_map = brw_state_batch(brw, size, 64, &brw->cc.blend_state_offset); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 struct GENX(BLEND_STATE) blend = { 0 }; { #else @@ -2969,7 +2969,7 @@ genX(upload_blend_state)(struct brw_context *brw) if (_mesa_is_multisample_enabled(ctx)) { if (ctx->Multisample.SampleAlphaToCoverage) { blend.AlphaToCoverageEnable = true; - blend.AlphaToCoverageDitherEnable = GEN_GEN >= 7; + blend.AlphaToCoverageDitherEnable = GFX_VER >= 7; } if (ctx->Multisample.SampleAlphaToOne) blend.AlphaToOneEnable = true; @@ -2987,7 +2987,7 @@ genX(upload_blend_state)(struct brw_context *brw) } } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 for (int i = 0; i < nr_draw_buffers; i++) { struct GENX(BLEND_STATE_ENTRY) entry = { 0 }; #else @@ -3023,7 +3023,7 @@ genX(upload_blend_state)(struct brw_context *brw) entry.WriteDisableBlue = !GET_COLORMASK_BIT(ctx->Color.ColorMask, i, 2); entry.WriteDisableAlpha = !GET_COLORMASK_BIT(ctx->Color.ColorMask, i, 3); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 GENX(BLEND_STATE_ENTRY_pack)(NULL, &blend_map[1 + i * 2], &entry); #else GENX(BLEND_STATE_ENTRY_pack)(NULL, &blend_map[i * 2], &entry); @@ -3031,11 +3031,11 @@ genX(upload_blend_state)(struct brw_context *brw) } } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 GENX(BLEND_STATE_pack)(NULL, blend_map, &blend); #endif -#if GEN_GEN < 7 +#if GFX_VER < 7 brw_batch_emit(brw, GENX(3DSTATE_CC_STATE_POINTERS), ptr) { ptr.PointertoBLEND_STATE = brw->cc.blend_state_offset; ptr.BLEND_STATEChange = true; @@ -3043,7 +3043,7 @@ genX(upload_blend_state)(struct brw_context *brw) #else brw_batch_emit(brw, GENX(3DSTATE_BLEND_STATE_POINTERS), ptr) { ptr.BlendStatePointer = brw->cc.blend_state_offset; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 ptr.BlendStatePointerValid = true; #endif } @@ -3066,7 +3066,7 @@ UNUSED static const struct brw_tracked_state genX(blend_state) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 7 +#if GFX_VER >= 7 UNUSED static const uint32_t push_constant_opcodes[] = { [MESA_SHADER_VERTEX] = 21, [MESA_SHADER_TESS_CTRL] = 25, /* HS */ @@ -3082,7 +3082,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw) const struct gen_device_info *devinfo = &brw->screen->devinfo; struct gl_context *ctx = &brw->ctx; - UNUSED uint32_t mocs = GEN_GEN < 8 ? GEN7_MOCS_L3 : 0; + UNUSED uint32_t mocs = GFX_VER < 8 ? GEN7_MOCS_L3 : 0; struct brw_stage_state *stage_states[] = { &brw->vs.base, @@ -3172,7 +3172,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw) } stage_state->push_constants_dirty = false; - brw->ctx.NewDriverState |= GEN_GEN >= 9 ? BRW_NEW_SURFACES : 0; + brw->ctx.NewDriverState |= GFX_VER >= 9 ? BRW_NEW_SURFACES : 0; } } @@ -3185,7 +3185,7 @@ const struct brw_tracked_state genX(push_constant_packets) = { }; #endif -#if GEN_GEN >= 6 +#if GFX_VER >= 6 static void genX(upload_vs_push_constants)(struct brw_context *brw) { @@ -3263,7 +3263,7 @@ static const struct brw_tracked_state genX(wm_push_constants) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 6 +#if GFX_VER >= 6 static unsigned genX(determine_sample_mask)(struct brw_context *brw) { @@ -3305,9 +3305,9 @@ genX(emit_3dstate_multisample2)(struct brw_context *brw, brw_batch_emit(brw, GENX(3DSTATE_MULTISAMPLE), multi) { multi.PixelLocation = CENTER; multi.NumberofMultisamples = log2_samples; -#if GEN_GEN == 6 +#if GFX_VER == 6 INTEL_SAMPLE_POS_4X(multi.Sample); -#elif GEN_GEN == 7 +#elif GFX_VER == 7 switch (num_samples) { case 1: INTEL_SAMPLE_POS_1X(multi.Sample); @@ -3343,7 +3343,7 @@ genX(upload_multisample_state)(struct brw_context *brw) static const struct brw_tracked_state genX(multisample_state) = { .dirty = { .mesa = _NEW_MULTISAMPLE | - (GEN_GEN == 10 ? _NEW_BUFFERS : 0), + (GFX_VER == 10 ? _NEW_BUFFERS : 0), .brw = BRW_NEW_BLORP | BRW_NEW_CONTEXT | BRW_NEW_NUM_SAMPLES, @@ -3360,7 +3360,7 @@ genX(upload_color_calc_state)(struct brw_context *brw) struct gl_context *ctx = &brw->ctx; brw_state_emit(brw, GENX(COLOR_CALC_STATE), 64, &brw->cc.state_offset, cc) { -#if GEN_GEN <= 5 +#if GFX_VER <= 5 cc.IndependentAlphaBlendEnable = set_blend_entry_bits(brw, &cc, 0, false); set_depth_stencil_bits(brw, &cc); @@ -3385,7 +3385,7 @@ genX(upload_color_calc_state)(struct brw_context *brw) cc.BlendConstantColorBlue = ctx->Color.BlendColorUnclamped[2]; cc.BlendConstantColorAlpha = ctx->Color.BlendColorUnclamped[3]; -#if GEN_GEN < 9 +#if GFX_VER < 9 /* _NEW_STENCIL */ cc.StencilReferenceValue = _mesa_get_stencil_ref(ctx, 0); cc.BackfaceStencilReferenceValue = @@ -3399,10 +3399,10 @@ genX(upload_color_calc_state)(struct brw_context *brw) ctx->Color.AlphaRef); } -#if GEN_GEN >= 6 +#if GFX_VER >= 6 brw_batch_emit(brw, GENX(3DSTATE_CC_STATE_POINTERS), ptr) { ptr.ColorCalcStatePointer = brw->cc.state_offset; -#if GEN_GEN != 7 +#if GFX_VER != 7 ptr.ColorCalcStatePointerValid = true; #endif } @@ -3415,12 +3415,12 @@ UNUSED static const struct brw_tracked_state genX(color_calc_state) = { .dirty = { .mesa = _NEW_COLOR | _NEW_STENCIL | - (GEN_GEN <= 5 ? _NEW_BUFFERS | + (GFX_VER <= 5 ? _NEW_BUFFERS | _NEW_DEPTH : 0), .brw = BRW_NEW_BATCH | BRW_NEW_BLORP | - (GEN_GEN <= 5 ? BRW_NEW_CC_VP | + (GFX_VER <= 5 ? BRW_NEW_CC_VP | BRW_NEW_STATS_WM : BRW_NEW_CC_STATE | BRW_NEW_STATE_BASE_ADDRESS), @@ -3460,7 +3460,7 @@ static const struct brw_tracked_state genX(cc_and_blend_state) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void genX(upload_sbe)(struct brw_context *brw) { @@ -3470,7 +3470,7 @@ genX(upload_sbe)(struct brw_context *brw) /* BRW_NEW_FS_PROG_DATA */ const struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(brw->wm.base.prog_data); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 struct GENX(SF_OUTPUT_ATTRIBUTE_DETAIL) attr_overrides[16] = { { 0 } }; #else #define attr_overrides sbe.Attribute @@ -3520,19 +3520,19 @@ genX(upload_sbe)(struct brw_context *brw) sbe.PointSpriteTextureCoordinateEnable = point_sprite_enables; sbe.ConstantInterpolationEnable = wm_prog_data->flat_inputs; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 sbe.ForceVertexURBEntryReadLength = true; sbe.ForceVertexURBEntryReadOffset = true; #endif -#if GEN_GEN >= 9 +#if GFX_VER >= 9 /* prepare the active component dwords */ for (int i = 0; i < 32; i++) sbe.AttributeActiveComponentFormat[i] = ACTIVE_COMPONENT_XYZW; #endif } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 brw_batch_emit(brw, GENX(3DSTATE_SBE_SWIZ), sbes) { for (int i = 0; i < 16; i++) sbes.Attribute[i] = attr_overrides[i]; @@ -3556,7 +3556,7 @@ static const struct brw_tracked_state genX(sbe_state) = { BRW_NEW_GS_PROG_DATA | BRW_NEW_TES_PROG_DATA | BRW_NEW_VUE_MAP_GEOM_OUT | - (GEN_GEN == 7 ? BRW_NEW_PRIMITIVE + (GFX_VER == 7 ? BRW_NEW_PRIMITIVE : 0), }, .emit = genX(upload_sbe), @@ -3565,7 +3565,7 @@ static const struct brw_tracked_state genX(sbe_state) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 7 +#if GFX_VER >= 7 /** * Outputs the 3DSTATE_SO_DECL_LIST command. * @@ -3671,13 +3671,13 @@ genX(upload_3dstate_so_buffers)(struct brw_context *brw) /* BRW_NEW_TRANSFORM_FEEDBACK */ struct gl_transform_feedback_object *xfb_obj = ctx->TransformFeedback.CurrentObject; -#if GEN_GEN < 8 +#if GFX_VER < 8 const struct gl_transform_feedback_info *linked_xfb_info = xfb_obj->program->sh.LinkedTransformFeedback; #else struct brw_transform_feedback_object *brw_obj = (struct brw_transform_feedback_object *) xfb_obj; - uint32_t mocs_wb = GEN_GEN >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; + uint32_t mocs_wb = GFX_VER >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB; #endif /* Set up the up to 4 output buffers. These are the ranges defined in the @@ -3706,7 +3706,7 @@ genX(upload_3dstate_so_buffers)(struct brw_context *brw) sob.SOBufferIndex = i; sob.SurfaceBaseAddress = rw_bo(bo, start); -#if GEN_GEN < 8 +#if GFX_VER < 8 sob.SurfacePitch = linked_xfb_info->Buffers[i].Stride * 4; sob.SurfaceEndAddress = rw_bo(bo, end); #else @@ -3730,7 +3730,7 @@ genX(upload_3dstate_so_buffers)(struct brw_context *brw) } } -#if GEN_GEN >= 8 +#if GFX_VER >= 8 brw_obj->zero_offsets = false; #endif } @@ -3773,7 +3773,7 @@ genX(upload_3dstate_streamout)(struct brw_context *brw, bool active, if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) sos.ReorderMode = TRAILING; -#if GEN_GEN < 8 +#if GFX_VER < 8 sos.SOBufferEnable0 = xfb_obj->Buffers[0] != NULL; sos.SOBufferEnable1 = xfb_obj->Buffers[1] != NULL; sos.SOBufferEnable2 = xfb_obj->Buffers[2] != NULL; @@ -3845,7 +3845,7 @@ static const struct brw_tracked_state genX(sol_state) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void genX(upload_ps)(struct brw_context *brw) { @@ -3857,7 +3857,7 @@ genX(upload_ps)(struct brw_context *brw) brw_wm_prog_data(brw->wm.base.prog_data); const struct brw_stage_state *stage_state = &brw->wm.base; -#if GEN_GEN < 8 +#if GFX_VER < 8 #endif brw_batch_emit(brw, GENX(3DSTATE_PS), ps) { @@ -3865,14 +3865,14 @@ genX(upload_ps)(struct brw_context *brw) * incorrect for subspans where some of the pixels are unlit. We believe * the bit just didn't take effect in previous generations. */ - ps.VectorMaskEnable = GEN_GEN >= 8; + ps.VectorMaskEnable = GFX_VER >= 8; /* WA_1606682166: * "Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes. * Disable the Sampler state prefetch functionality in the SARB by * programming 0xB000[30] to '1'." */ - ps.SamplerCount = GEN_GEN == 11 ? + ps.SamplerCount = GFX_VER == 11 ? 0 : DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4); /* BRW_NEW_FS_PROG_DATA */ @@ -3897,9 +3897,9 @@ genX(upload_ps)(struct brw_context *brw) * * In Gen8 the format is U8-2 whereas in Gen9+ it is U9-1. */ -#if GEN_GEN >= 9 +#if GFX_VER >= 9 ps.MaximumNumberofThreadsPerPSD = 64 - 1; -#elif GEN_GEN >= 8 +#elif GFX_VER >= 8 ps.MaximumNumberofThreadsPerPSD = 64 - 2; #else ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1; @@ -3909,7 +3909,7 @@ genX(upload_ps)(struct brw_context *brw) prog_data->base.ubo_ranges[0].length > 0) ps.PushConstantEnable = true; -#if GEN_GEN < 8 +#if GFX_VER < 8 /* From the IVB PRM, volume 2 part 1, page 287: * "This bit is inserted in the PS payload header and made available to * the DataPort (either via the message header or via header bypass) to @@ -3964,7 +3964,7 @@ genX(upload_ps)(struct brw_context *brw) * * BRW_NEW_NUM_SAMPLES */ - if (GEN_GEN >= 9 && !prog_data->persample_dispatch && + if (GFX_VER >= 9 && !prog_data->persample_dispatch && brw->num_samples == 16) { assert(ps._8PixelDispatchEnable || ps._16PixelDispatchEnable); ps._32PixelDispatchEnable = false; @@ -3995,13 +3995,13 @@ genX(upload_ps)(struct brw_context *brw) static const struct brw_tracked_state genX(ps_state) = { .dirty = { .mesa = _NEW_MULTISAMPLE | - (GEN_GEN < 8 ? _NEW_BUFFERS | + (GFX_VER < 8 ? _NEW_BUFFERS | _NEW_COLOR : 0), .brw = BRW_NEW_BATCH | BRW_NEW_BLORP | BRW_NEW_FS_PROG_DATA | - (GEN_GEN >= 9 ? BRW_NEW_NUM_SAMPLES : 0), + (GFX_VER >= 9 ? BRW_NEW_NUM_SAMPLES : 0), }, .emit = genX(upload_ps), }; @@ -4009,7 +4009,7 @@ static const struct brw_tracked_state genX(ps_state) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void genX(upload_hs_state)(struct brw_context *brw) { @@ -4034,7 +4034,7 @@ genX(upload_hs_state)(struct brw_context *brw) hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 hs.DispatchMode = vue_prog_data->dispatch_mode; hs.IncludePrimitiveID = tcs_prog_data->include_primitive_id; #endif @@ -4069,7 +4069,7 @@ genX(upload_ds_state)(struct brw_context *brw) if (!tes_prog_data) { brw_batch_emit(brw, GENX(3DSTATE_DS), ds); } else { - assert(GEN_GEN < 11 || + assert(GFX_VER < 11 || vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8); brw_batch_emit(brw, GENX(3DSTATE_DS), ds) { @@ -4079,7 +4079,7 @@ genX(upload_ds_state)(struct brw_context *brw) ds.ComputeWCoordinateEnable = tes_prog_data->domain == BRW_TESS_DOMAIN_TRI; -#if GEN_GEN >= 8 +#if GFX_VER >= 8 if (vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8) ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH; ds.UserClipDistanceCullTestEnableBitmask = @@ -4191,7 +4191,7 @@ static const struct brw_tracked_state genX(tcs_push_constants) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void genX(upload_cs_push_constants)(struct brw_context *brw) { @@ -4300,7 +4300,7 @@ genX(upload_cs_state)(struct brw_context *brw) if (prog_data->total_scratch) { uint32_t per_thread_scratch_value; - if (GEN_GEN >= 8) { + if (GFX_VER >= 8) { /* Broadwell's Per Thread Scratch Space is in the range [0, 11] * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M. */ @@ -4329,15 +4329,15 @@ genX(upload_cs_state)(struct brw_context *brw) */ const uint32_t subslices = MAX2(brw->screen->subslice_total, 1); vfe.MaximumNumberofThreads = devinfo->max_cs_threads * subslices - 1; - vfe.NumberofURBEntries = GEN_GEN >= 8 ? 2 : 0; -#if GEN_GEN < 11 + vfe.NumberofURBEntries = GFX_VER >= 8 ? 2 : 0; +#if GFX_VER < 11 vfe.ResetGatewayTimer = Resettingrelativetimerandlatchingtheglobaltimestamp; #endif -#if GEN_GEN < 9 +#if GFX_VER < 9 vfe.BypassGatewayControl = BypassingOpenGatewayCloseGatewayprotocol; #endif -#if GEN_GEN == 7 +#if GFX_VER == 7 vfe.GPGPUMode = 1; #endif @@ -4359,7 +4359,7 @@ genX(upload_cs_state)(struct brw_context *brw) * Note: The constant data is built in brw_upload_cs_push_constants * below. */ - vfe.URBEntryAllocationSize = GEN_GEN >= 8 ? 2 : 0; + vfe.URBEntryAllocationSize = GFX_VER >= 8 ? 2 : 0; const uint32_t vfe_curbe_allocation = ALIGN(cs_prog_data->push.per_thread.regs * cs_params.threads + @@ -4386,12 +4386,12 @@ genX(upload_cs_state)(struct brw_context *brw) .KernelStartPointer = ksp, .SamplerStatePointer = stage_state->sampler_offset, /* WA_1606682166 */ - .SamplerCount = GEN_GEN == 11 ? 0 : + .SamplerCount = GFX_VER == 11 ? 0 : DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4), .BindingTablePointer = stage_state->bind_bo_offset, .ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs, .NumberofThreadsinGPGPUThreadGroup = cs_params.threads, - .SharedLocalMemorySize = encode_slm_size(GEN_GEN, + .SharedLocalMemorySize = encode_slm_size(GFX_VER, prog_data->total_shared), .BarrierEnable = cs_prog_data->uses_barrier, #if GFX_VERx10 >= 75 @@ -4438,7 +4438,7 @@ prepare_indirect_gpgpu_walker(struct brw_context *brw) emit_lrm(brw, GPGPU_DISPATCHDIMY, ro_bo(bo, indirect_offset + 4)); emit_lrm(brw, GPGPU_DISPATCHDIMZ, ro_bo(bo, indirect_offset + 8)); -#if GEN_GEN <= 7 +#if GFX_VER <= 7 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */ emit_lri(brw, MI_PREDICATE_SRC0 + 4, 0); emit_lri(brw, MI_PREDICATE_SRC1 , 0); @@ -4500,7 +4500,7 @@ genX(emit_gpgpu_walker)(struct brw_context *brw) brw_batch_emit(brw, GENX(GPGPU_WALKER), ggw) { ggw.IndirectParameterEnable = indirect; - ggw.PredicateEnable = GEN_GEN <= 7 && indirect; + ggw.PredicateEnable = GFX_VER <= 7 && indirect; ggw.SIMDSize = cs_params.simd_size / 16; ggw.ThreadDepthCounterMaximum = 0; ggw.ThreadHeightCounterMaximum = 0; @@ -4519,7 +4519,7 @@ genX(emit_gpgpu_walker)(struct brw_context *brw) /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 static void genX(upload_raster)(struct brw_context *brw) { @@ -4596,7 +4596,7 @@ genX(upload_raster)(struct brw_context *brw) /* _NEW_LINE */ raster.AntialiasingEnable = ctx->Line.SmoothFlag; -#if GEN_GEN == 10 +#if GFX_VER == 10 /* _NEW_BUFFERS * Antialiasing Enable bit MUST not be set when NUM_MULTISAMPLES > 1. */ @@ -4610,13 +4610,13 @@ genX(upload_raster)(struct brw_context *brw) raster.ScissorRectangleEnable = ctx->Scissor.EnableFlags; /* _NEW_TRANSFORM */ -#if GEN_GEN < 9 +#if GFX_VER < 9 if (!(ctx->Transform.DepthClampNear && ctx->Transform.DepthClampFar)) raster.ViewportZClipTestEnable = true; #endif -#if GEN_GEN >= 9 +#if GFX_VER >= 9 if (!ctx->Transform.DepthClampNear) raster.ViewportZNearClipTestEnable = true; @@ -4625,7 +4625,7 @@ genX(upload_raster)(struct brw_context *brw) #endif /* BRW_NEW_CONSERVATIVE_RASTERIZATION */ -#if GEN_GEN >= 9 +#if GFX_VER >= 9 raster.ConservativeRasterizationEnable = ctx->IntelConservativeRasterization; #endif @@ -4656,7 +4656,7 @@ static const struct brw_tracked_state genX(raster_state) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 static void genX(upload_ps_extra)(struct brw_context *brw) { @@ -4676,7 +4676,7 @@ genX(upload_ps_extra)(struct brw_context *brw) /* _NEW_MULTISAMPLE | BRW_NEW_CONSERVATIVE_RASTERIZATION */ if (prog_data->uses_sample_mask) { -#if GEN_GEN >= 9 +#if GFX_VER >= 9 if (prog_data->post_depth_coverage) psx.InputCoverageMaskState = ICMS_DEPTH_COVERAGE; else if (prog_data->inner_coverage && ctx->IntelConservativeRasterization) @@ -4689,7 +4689,7 @@ genX(upload_ps_extra)(struct brw_context *brw) } psx.oMaskPresenttoRenderTarget = prog_data->uses_omask; -#if GEN_GEN >= 9 +#if GFX_VER >= 9 psx.PixelShaderPullsBary = prog_data->pulls_bary; psx.PixelShaderComputesStencil = prog_data->computed_stencil; #endif @@ -4745,7 +4745,7 @@ const struct brw_tracked_state genX(ps_extra) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 static void genX(upload_ps_blend)(struct brw_context *brw) { @@ -4871,7 +4871,7 @@ static const struct brw_tracked_state genX(ps_blend) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 8 +#if GFX_VER >= 8 static void genX(emit_vf_topology)(struct brw_context *brw) { @@ -4892,7 +4892,7 @@ static const struct brw_tracked_state genX(vf_topology) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void genX(emit_mi_report_perf_count)(struct brw_context *brw, struct brw_bo *bo, @@ -4915,7 +4915,7 @@ static void genX(emit_sampler_state_pointers_xs)(UNUSED struct brw_context *brw, UNUSED struct brw_stage_state *stage_state) { -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static const uint16_t packet_headers[] = { [MESA_SHADER_VERTEX] = 43, [MESA_SHADER_TESS_CTRL] = 44, @@ -5011,7 +5011,7 @@ genX(upload_default_color)(struct brw_context *brw, color.ui[3] = float_as_int(1.0); int alignment = 32; - if (GEN_GEN >= 8) { + if (GFX_VER >= 8) { alignment = 64; } else if (GFX_VERx10 == 75 && (is_integer_format || is_stencil_sampling)) { alignment = 512; @@ -5044,7 +5044,7 @@ genX(upload_default_color)(struct brw_context *brw, macro(state.BorderColor ## _color_type ## Blue, src[2]); \ macro(state.BorderColor ## _color_type ## Alpha, src[3]); -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* On Broadwell, the border color is represented as four 32-bit floats, * integers, or unsigned values, interpreted according to the surface * format. This matches the sampler->BorderColor union exactly; just @@ -5099,7 +5099,7 @@ genX(upload_default_color)(struct brw_context *brw, } else { BORDER_COLOR_ATTR(ASSIGN, Float, color.f); } -#elif GEN_GEN == 5 || GEN_GEN == 6 +#elif GFX_VER == 5 || GFX_VER == 6 BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_UBYTE, Unorm, color.f); BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_USHORT, Unorm16, color.f); BORDER_COLOR_ATTR(UNCLAMPED_FLOAT_TO_SHORT, Snorm16, color.f); @@ -5117,7 +5117,7 @@ genX(upload_default_color)(struct brw_context *brw, state.BorderColorSnorm8Alpha = state.BorderColorSnorm16Alpha >> 8; BORDER_COLOR_ATTR(ASSIGN, Float, color.f); -#elif GEN_GEN == 4 +#elif GFX_VER == 4 BORDER_COLOR_ATTR(ASSIGN, , color.f); #else BORDER_COLOR_ATTR(ASSIGN, Float, color.f); @@ -5136,7 +5136,7 @@ translate_wrap_mode(GLenum wrap, UNUSED bool using_nearest) case GL_REPEAT: return TCM_WRAP; case GL_CLAMP: -#if GEN_GEN >= 8 +#if GFX_VER >= 8 /* GL_CLAMP is the weird mode where coordinates are clamped to * [0.0, 1.0], so linear filtering of coordinates outside of * [0.0, 1.0] give you half edge texel value and half border @@ -5176,7 +5176,7 @@ translate_wrap_mode(GLenum wrap, UNUSED bool using_nearest) static bool wrap_mode_needs_border_color(unsigned wrap_mode) { -#if GEN_GEN >= 8 +#if GFX_VER >= 8 return wrap_mode == TCM_CLAMP_BORDER || wrap_mode == TCM_HALF_BORDER; #else @@ -5302,24 +5302,24 @@ genX(update_sampler_state)(struct brw_context *brw, sampler->Attrib.CompareMode == GL_COMPARE_R_TO_TEXTURE_ARB ? brw_translate_shadow_compare_func(sampler->Attrib.CompareFunc) : 0; -#if GEN_GEN >= 7 +#if GFX_VER >= 7 /* Set shadow function. */ samp_st.AnisotropicAlgorithm = samp_st.MinModeFilter == MAPFILTER_ANISOTROPIC ? EWAApproximation : LEGACY; #endif -#if GEN_GEN >= 6 +#if GFX_VER >= 6 samp_st.NonnormalizedCoordinateEnable = target == GL_TEXTURE_RECTANGLE; #endif - const float hw_max_lod = GEN_GEN >= 7 ? 14 : 13; + const float hw_max_lod = GFX_VER >= 7 ? 14 : 13; samp_st.MinLOD = CLAMP(sampler->Attrib.MinLod, 0, hw_max_lod); samp_st.MaxLOD = CLAMP(sampler->Attrib.MaxLod, 0, hw_max_lod); samp_st.TextureLODBias = CLAMP(tex_unit_lod_bias + sampler->Attrib.LodBias, -16, 15); -#if GEN_GEN == 6 +#if GFX_VER == 6 samp_st.BaseMipLevel = CLAMP(texObj->Attrib.MinLevel + texObj->Attrib.BaseLevel, 0, hw_max_lod); samp_st.MinandMagStateNotEqual = @@ -5339,14 +5339,14 @@ genX(update_sampler_state)(struct brw_context *brw, texObj->StencilSampling, &border_color_offset); } -#if GEN_GEN < 6 +#if GFX_VER < 6 samp_st.BorderColorPointer = ro_bo(brw->batch.state.bo, border_color_offset); #else samp_st.BorderColorPointer = border_color_offset; #endif -#if GEN_GEN >= 8 +#if GFX_VER >= 8 samp_st.LODPreClampMode = CLAMP_MODE_OGL; #else samp_st.LODPreClampEnable = true; @@ -5411,7 +5411,7 @@ genX(upload_sampler_state_table)(struct brw_context *brw, sampler_state += dwords; } - if (GEN_GEN >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) { + if (GFX_VER >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) { /* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */ genX(emit_sampler_state_pointers_xs)(brw, stage_state); } else { @@ -5458,7 +5458,7 @@ static const struct brw_tracked_state genX(vs_samplers) = { .emit = genX(upload_vs_samplers), }; -#if GEN_GEN >= 6 +#if GFX_VER >= 6 static void genX(upload_gs_samplers)(struct brw_context *brw) { @@ -5482,7 +5482,7 @@ static const struct brw_tracked_state genX(gs_samplers) = { }; #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void genX(upload_tcs_samplers)(struct brw_context *brw) { @@ -5505,7 +5505,7 @@ static const struct brw_tracked_state genX(tcs_samplers) = { }; #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void genX(upload_tes_samplers)(struct brw_context *brw) { @@ -5528,7 +5528,7 @@ static const struct brw_tracked_state genX(tes_samplers) = { }; #endif -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static void genX(upload_cs_samplers)(struct brw_context *brw) { @@ -5553,7 +5553,7 @@ const struct brw_tracked_state genX(cs_samplers) = { /* ---------------------------------------------------------------------- */ -#if GEN_GEN <= 5 +#if GFX_VER <= 5 static void genX(upload_blend_constant_color)(struct brw_context *brw) { @@ -5582,7 +5582,7 @@ static const struct brw_tracked_state genX(blend_constant_color) = { void genX(init_atoms)(struct brw_context *brw) { -#if GEN_GEN < 6 +#if GFX_VER < 6 static const struct brw_tracked_state *render_atoms[] = { &genX(vf_statistics), @@ -5640,7 +5640,7 @@ genX(init_atoms)(struct brw_context *brw) &brw_constant_buffer }; -#elif GEN_GEN == 6 +#elif GFX_VER == 6 static const struct brw_tracked_state *render_atoms[] = { &genX(vf_statistics), @@ -5706,7 +5706,7 @@ genX(init_atoms)(struct brw_context *brw) &genX(index_buffer), &genX(vertices), }; -#elif GEN_GEN == 7 +#elif GFX_VER == 7 static const struct brw_tracked_state *render_atoms[] = { &genX(vf_statistics), @@ -5802,7 +5802,7 @@ genX(init_atoms)(struct brw_context *brw) &genX(cut_index), #endif }; -#elif GEN_GEN >= 8 +#elif GFX_VER >= 8 static const struct brw_tracked_state *render_atoms[] = { &genX(vf_statistics), @@ -5902,7 +5902,7 @@ genX(init_atoms)(struct brw_context *brw) brw_copy_pipeline_atoms(brw, BRW_RENDER_PIPELINE, render_atoms, ARRAY_SIZE(render_atoms)); -#if GEN_GEN >= 7 +#if GFX_VER >= 7 static const struct brw_tracked_state *compute_atoms[] = { &gen7_l3_state,