radeon/uvd: add uvd soc15 register
Signed-off-by: Leo Liu <leo.liu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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@ -91,6 +91,12 @@ struct ruvd_decoder {
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bool use_legacy;
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struct rvid_buffer ctx;
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struct rvid_buffer sessionctx;
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struct {
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unsigned data0;
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unsigned data1;
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unsigned cmd;
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unsigned cntl;
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} reg;
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};
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/* flush IB to the hardware */
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@ -120,14 +126,14 @@ static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
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uint64_t addr;
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addr = dec->ws->buffer_get_virtual_address(buf);
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addr = addr + off;
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set_reg(dec, RUVD_GPCOM_VCPU_DATA0, addr);
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set_reg(dec, RUVD_GPCOM_VCPU_DATA1, addr >> 32);
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set_reg(dec, dec->reg.data0, addr);
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set_reg(dec, dec->reg.data1, addr >> 32);
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} else {
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off += dec->ws->buffer_get_reloc_offset(buf);
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set_reg(dec, RUVD_GPCOM_VCPU_DATA0, off);
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set_reg(dec, RUVD_GPCOM_VCPU_DATA1, reloc_idx * 4);
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}
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set_reg(dec, RUVD_GPCOM_VCPU_CMD, cmd << 1);
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set_reg(dec, dec->reg.cmd, cmd << 1);
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}
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/* do the codec needs an IT buffer ?*/
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@ -1150,7 +1156,7 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
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if (have_it(dec))
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send_cmd(dec, RUVD_CMD_ITSCALING_TABLE_BUFFER, msg_fb_it_buf->res->buf,
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FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
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set_reg(dec, RUVD_ENGINE_CNTL, 1);
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set_reg(dec, dec->reg.cntl, 1);
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flush(dec, RADEON_FLUSH_ASYNC);
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next_buffer(dec);
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@ -1284,6 +1290,18 @@ struct pipe_video_codec *ruvd_create_decoder(struct pipe_context *context,
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rvid_clear_buffer(context, &dec->sessionctx);
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}
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if (info.family >= CHIP_VEGA10) {
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dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0_SOC15;
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dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1_SOC15;
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dec->reg.cmd = RUVD_GPCOM_VCPU_CMD_SOC15;
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dec->reg.cntl = RUVD_ENGINE_CNTL_SOC15;
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} else {
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dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0;
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dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1;
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dec->reg.cmd = RUVD_GPCOM_VCPU_CMD;
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dec->reg.cntl = RUVD_ENGINE_CNTL;
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}
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map_msg_fb_it_buf(dec);
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dec->msg->size = sizeof(*dec->msg);
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dec->msg->msg_type = RUVD_MSG_CREATE;
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@ -56,6 +56,11 @@
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#define RUVD_GPCOM_VCPU_DATA1 0xEF14
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#define RUVD_ENGINE_CNTL 0xEF18
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#define RUVD_GPCOM_VCPU_CMD_SOC15 0x2070c
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#define RUVD_GPCOM_VCPU_DATA0_SOC15 0x20710
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#define RUVD_GPCOM_VCPU_DATA1_SOC15 0x20714
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#define RUVD_ENGINE_CNTL_SOC15 0x20718
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/* UVD commands to VCPU */
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#define RUVD_CMD_MSG_BUFFER 0x00000000
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#define RUVD_CMD_DPB_BUFFER 0x00000001
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