i965/vec4/nir: fix emitting 64-bit immediates
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
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@ -352,8 +352,15 @@ vec4_visitor::get_indirect_offset(nir_intrinsic_instr *instr)
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void
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vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
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{
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dst_reg reg = dst_reg(VGRF, alloc.allocate(1));
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reg.type = BRW_REGISTER_TYPE_D;
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dst_reg reg;
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if (instr->def.bit_size == 64) {
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reg = dst_reg(VGRF, alloc.allocate(2));
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reg.type = BRW_REGISTER_TYPE_DF;
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} else {
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reg = dst_reg(VGRF, alloc.allocate(1));
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reg.type = BRW_REGISTER_TYPE_D;
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}
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unsigned remaining = brw_writemask_for_size(instr->def.num_components);
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@ -368,13 +375,20 @@ vec4_visitor::nir_emit_load_const(nir_load_const_instr *instr)
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continue;
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for (unsigned j = i; j < instr->def.num_components; j++) {
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if (instr->value.u32[i] == instr->value.u32[j]) {
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if ((instr->def.bit_size == 32 &&
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instr->value.u32[i] == instr->value.u32[j]) ||
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(instr->def.bit_size == 64 &&
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instr->value.f64[i] == instr->value.f64[j])) {
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writemask |= 1 << j;
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}
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}
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reg.writemask = writemask;
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emit(MOV(reg, brw_imm_d(instr->value.i32[i])));
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if (instr->def.bit_size == 64) {
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emit(MOV(reg, brw_imm_df(instr->value.f64[i])));
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} else {
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emit(MOV(reg, brw_imm_d(instr->value.i32[i])));
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}
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remaining &= ~writemask;
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}
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