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radv: reset VRS if the current subpass doesn't have a VRS attachment 

With a scenario like:
BeginRP(DS + VRS att)
Draw()
EndRP()
BeginRP(same DS)
Draw()
EndRP()

The second draw shouldn't use VRS but it did because the VRS bit
is always set during DS surface initialization if a surface can use VRS.
So, it would have been using the previous copied VRS rates.

Found by inspection.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14443>
This commit is contained in:
Samuel Pitoiset 2022-01-07 09:56:48 +01:00 committed by Marge Bot
parent ec4dcd53db
commit 9c746157ae
1 changed files with 6 additions and 1 deletions
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7
src/amd/vulkan/radv_cmd_buffer.c
View File

@ -1920,6 +1920,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_
const struct radv_image *image = iview->image;
uint32_t db_z_info = ds->db_z_info;
uint32_t db_stencil_info = ds->db_stencil_info;
uint32_t db_htile_surface = ds->db_htile_surface;
if (!radv_layout_is_htile_compressed(
cmd_buffer->device, image, layout, in_render_loop,
@ -1929,8 +1930,12 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_
db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
}
if (!cmd_buffer->state.subpass->vrs_attachment) {
db_htile_surface &= C_028ABC_VRS_HTILE_ENCODING;
}
radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);