From 9c5a2ab6a9d8ffe61178a0f0850deacafb2ff155 Mon Sep 17 00:00:00 2001 From: Mike Blumenkrantz Date: Tue, 15 Jun 2021 11:35:02 -0400 Subject: [PATCH] zink: convert rasterizer pipeline components to bitfield this reduces the hashed pipeline key size by 53 bits Reviewed-by: Dave Airlie Part-of: --- src/gallium/drivers/zink/zink_pipeline.c | 19 ++++++++++--------- src/gallium/drivers/zink/zink_pipeline.h | 3 ++- src/gallium/drivers/zink/zink_state.c | 23 ++++++++++++----------- src/gallium/drivers/zink/zink_state.h | 2 ++ 4 files changed, 26 insertions(+), 21 deletions(-) diff --git a/src/gallium/drivers/zink/zink_pipeline.c b/src/gallium/drivers/zink/zink_pipeline.c index b7373a315d4..51c250340e9 100644 --- a/src/gallium/drivers/zink/zink_pipeline.c +++ b/src/gallium/drivers/zink/zink_pipeline.c @@ -51,6 +51,7 @@ zink_create_gfx_pipeline(struct zink_screen *screen, struct zink_gfx_pipeline_state *state, VkPrimitiveTopology primitive_topology) { + struct zink_rasterizer_hw_state *hw_rast_state = (void*)state; VkPipelineVertexInputStateCreateInfo vertex_input_state; if (!screen->info.have_EXT_vertex_input_dynamic_state) { memset(&vertex_input_state, 0, sizeof(vertex_input_state)); @@ -118,7 +119,7 @@ zink_create_gfx_pipeline(struct zink_screen *screen, ms_state.alphaToCoverageEnable = state->blend_state->alpha_to_coverage; ms_state.alphaToOneEnable = state->blend_state->alpha_to_one; ms_state.pSampleMask = state->sample_mask ? &state->sample_mask : NULL; - if (state->rast_state->force_persample_interp) { + if (hw_rast_state->force_persample_interp) { ms_state.sampleShadingEnable = VK_TRUE; ms_state.minSampleShading = 1.0; } @@ -133,10 +134,10 @@ zink_create_gfx_pipeline(struct zink_screen *screen, VkPipelineRasterizationStateCreateInfo rast_state = {0}; rast_state.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO; - rast_state.depthClampEnable = state->rast_state->depth_clamp; - rast_state.rasterizerDiscardEnable = state->rast_state->rasterizer_discard; - rast_state.polygonMode = state->rast_state->polygon_mode; - rast_state.cullMode = state->rast_state->cull_mode; + rast_state.depthClampEnable = hw_rast_state->depth_clamp; + rast_state.rasterizerDiscardEnable = hw_rast_state->rasterizer_discard; + rast_state.polygonMode = hw_rast_state->polygon_mode; + rast_state.cullMode = hw_rast_state->cull_mode; rast_state.frontFace = state->dyn_state1.front_face; rast_state.depthBiasEnable = VK_TRUE; @@ -147,10 +148,10 @@ zink_create_gfx_pipeline(struct zink_screen *screen, VkPipelineRasterizationProvokingVertexStateCreateInfoEXT pv_state; pv_state.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_PROVOKING_VERTEX_STATE_CREATE_INFO_EXT; - pv_state.provokingVertexMode = state->rast_state->pv_last ? + pv_state.provokingVertexMode = hw_rast_state->pv_last ? VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT : VK_PROVOKING_VERTEX_MODE_FIRST_VERTEX_EXT; - if (screen->info.have_EXT_provoking_vertex && state->rast_state->pv_last) { + if (screen->info.have_EXT_provoking_vertex && hw_rast_state->pv_last) { pv_state.pNext = rast_state.pNext; rast_state.pNext = &pv_state; } @@ -206,9 +207,9 @@ zink_create_gfx_pipeline(struct zink_screen *screen, rast_line_state.sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT; rast_line_state.pNext = rast_state.pNext; rast_line_state.stippledLineEnable = VK_FALSE; - rast_line_state.lineRasterizationMode = state->rast_state->line_mode; + rast_line_state.lineRasterizationMode = hw_rast_state->line_mode; - if (state->rast_state->line_stipple_enable) { + if (hw_rast_state->line_stipple_enable) { dynamicStateEnables[state_count++] = VK_DYNAMIC_STATE_LINE_STIPPLE_EXT; rast_line_state.stippledLineEnable = VK_TRUE; } diff --git a/src/gallium/drivers/zink/zink_pipeline.h b/src/gallium/drivers/zink/zink_pipeline.h index 8d4d6bd273f..007901e189d 100644 --- a/src/gallium/drivers/zink/zink_pipeline.h +++ b/src/gallium/drivers/zink/zink_pipeline.h @@ -27,6 +27,7 @@ #include #include "pipe/p_state.h" +#include "zink_state.h" struct zink_blend_state; struct zink_depth_stencil_alpha_state; @@ -43,7 +44,7 @@ struct zink_gfx_pipeline_state { uint8_t void_alpha_attachments:PIPE_MAX_COLOR_BUFS; struct zink_blend_state *blend_state; - struct zink_rasterizer_hw_state *rast_state; + uint32_t rast_state : ZINK_RAST_HW_STATE_SIZE; //zink_rasterizer_hw_state VkSampleMask sample_mask; uint8_t rast_samples:7; diff --git a/src/gallium/drivers/zink/zink_state.c b/src/gallium/drivers/zink/zink_state.c index 19ed6b83bf4..e6d90644937 100644 --- a/src/gallium/drivers/zink/zink_state.c +++ b/src/gallium/drivers/zink/zink_state.c @@ -550,20 +550,21 @@ zink_bind_rasterizer_state(struct pipe_context *pctx, void *cso) bool clip_halfz = ctx->rast_state ? ctx->rast_state->base.clip_halfz : false; bool point_quad_rasterization = ctx->rast_state ? ctx->rast_state->base.point_quad_rasterization : false; bool scissor = ctx->rast_state ? ctx->rast_state->base.scissor : false; + bool pv_last = ctx->rast_state ? ctx->rast_state->hw_state.pv_last : false; ctx->rast_state = cso; if (ctx->rast_state) { - if (ctx->gfx_pipeline_state.rast_state != &ctx->rast_state->hw_state) { - if (screen->info.have_EXT_provoking_vertex && - (!ctx->gfx_pipeline_state.rast_state || - ctx->gfx_pipeline_state.rast_state->pv_last != ctx->rast_state->hw_state.pv_last) && - /* without this prop, change in pv mode requires new rp */ - !screen->info.pv_props.provokingVertexModePerPipeline) - zink_batch_no_rp(ctx); - ctx->gfx_pipeline_state.rast_state = &ctx->rast_state->hw_state; - ctx->gfx_pipeline_state.dirty = true; - ctx->rast_state_changed = true; - } + if (screen->info.have_EXT_provoking_vertex && + pv_last != ctx->rast_state->hw_state.pv_last && + /* without this prop, change in pv mode requires new rp */ + !screen->info.pv_props.provokingVertexModePerPipeline) + zink_batch_no_rp(ctx); + uint32_t rast_bits = 0; + memcpy(&rast_bits, &ctx->rast_state->hw_state, sizeof(struct zink_rasterizer_hw_state)); + ctx->gfx_pipeline_state.rast_state = rast_bits & BITFIELD_MASK(ZINK_RAST_HW_STATE_SIZE); + + ctx->gfx_pipeline_state.dirty = true; + ctx->rast_state_changed = true; if (clip_halfz != ctx->rast_state->base.clip_halfz) { ctx->last_vertex_stage_dirty = true; diff --git a/src/gallium/drivers/zink/zink_state.h b/src/gallium/drivers/zink/zink_state.h index 1fbaccdca6c..99ced31f4d9 100644 --- a/src/gallium/drivers/zink/zink_state.h +++ b/src/gallium/drivers/zink/zink_state.h @@ -65,6 +65,8 @@ struct zink_rasterizer_hw_state { bool force_persample_interp:1; bool clip_halfz:1; }; +#define ZINK_RAST_HW_STATE_SIZE 12 + struct zink_rasterizer_state { struct pipe_rasterizer_state base;