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radeon/llvm: Change the tablegen target from AMDIL to AMDGPU

This commit is contained in:
Tom Stellard 2012-07-27 17:46:40 +00:00
parent f56dfc3213
commit 9c42fb6f26
14 changed files with 119 additions and 107 deletions
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10
src/gallium/drivers/radeon/AMDILCodeEmitter.h → src/gallium/drivers/radeon/AMDGPUCodeEmitter.h
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@ -1,4 +1,4 @@
//===-- AMDILCodeEmitter.h - AMDIL Code Emitter interface -----------------===//
//===-- AMDGPUCodeEmitter.h - AMDGPU Code Emitter interface -----------------===//
//
// The LLVM Compiler Infrastructure
//
@ -11,12 +11,12 @@
//
//===----------------------------------------------------------------------===//
#ifndef AMDILCODEEMITTER_H
#define AMDILCODEEMITTER_H
#ifndef AMDGPUCODEEMITTER_H
#define AMDGPUCODEEMITTER_H
namespace llvm {
class AMDILCodeEmitter {
class AMDGPUCodeEmitter {
public:
uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
virtual uint64_t getMachineOpValue(const MachineInstr &MI,
@ -45,4 +45,4 @@ namespace llvm {
} // End namespace llvm
#endif // AMDILCODEEMITTER_H
#endif // AMDGPUCODEEMITTER_H

79
src/gallium/drivers/radeon/AMDGPUSubtarget.cpp Normal file
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@ -0,0 +1,79 @@
#include "AMDGPUSubtarget.h"
using namespace llvm;
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_TARGET_DESC
#include "AMDGPUGenSubtargetInfo.inc"
AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
AMDILSubtarget(TT, CPU, FS) {
InstrItins = getInstrItineraryForCPU(CPU);
memset(CapsOverride, 0, sizeof(*CapsOverride)
* AMDILDeviceInfo::MaxNumberCapabilities);
// Default card
std::string GPU = "rv770";
GPU = CPU;
mIs64bit = false;
mVersion = 0;
SmallVector<StringRef, DEFAULT_VEC_SLOTS> Features;
SplitString(FS, Features, ",");
mDefaultSize[0] = 64;
mDefaultSize[1] = 1;
mDefaultSize[2] = 1;
std::string newFeatures = "";
#if defined(_DEBUG) || defined(DEBUG)
bool useTest = false;
#endif
for (size_t x = 0; x < Features.size(); ++x) {
if (Features[x].startswith("+mwgs")) {
SmallVector<StringRef, DEFAULT_VEC_SLOTS> sizes;
SplitString(Features[x], sizes, "-");
size_t mDim = ::atoi(sizes[1].data());
if (mDim > 3) {
mDim = 3;
}
for (size_t y = 0; y < mDim; ++y) {
mDefaultSize[y] = ::atoi(sizes[y+2].data());
}
#if defined(_DEBUG) || defined(DEBUG)
} else if (!Features[x].compare("test")) {
useTest = true;
#endif
} else if (Features[x].startswith("+cal")) {
SmallVector<StringRef, DEFAULT_VEC_SLOTS> version;
SplitString(Features[x], version, "=");
mVersion = ::atoi(version[1].data());
} else {
GPU = CPU;
if (x > 0) newFeatures += ',';
newFeatures += Features[x];
}
}
// If we don't have a version then set it to
// -1 which enables everything. This is for
// offline devices.
if (!mVersion) {
mVersion = (uint32_t)-1;
}
for (int x = 0; x < 3; ++x) {
if (!mDefaultSize[x]) {
mDefaultSize[x] = 1;
}
}
#if defined(_DEBUG) || defined(DEBUG)
if (useTest) {
GPU = "kauai";
}
#endif
ParseSubtargetFeatures(GPU, newFeatures);
#if defined(_DEBUG) || defined(DEBUG)
if (useTest) {
GPU = "test";
}
#endif
mDevName = GPU;
mDevice = AMDILDeviceInfo::getDeviceFromName(mDevName, this, mIs64bit);
}

10
src/gallium/drivers/radeon/AMDGPUSubtarget.h
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@ -14,6 +14,8 @@
#ifndef _AMDGPUSUBTARGET_H_
#define _AMDGPUSUBTARGET_H_
#include "AMDILSubtarget.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
namespace llvm {
@ -22,13 +24,11 @@ class AMDGPUSubtarget : public AMDILSubtarget
InstrItineraryData InstrItins;
public:
AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
AMDILSubtarget(TT, CPU, FS)
{
InstrItins = getInstrItineraryForCPU(CPU);
}
AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
virtual void ParseSubtargetFeatures(llvm::StringRef CPU, llvm::StringRef FS);
};
} // End namespace llvm

9
src/gallium/drivers/radeon/AMDILBase.td
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@ -89,9 +89,10 @@ def AMDILInstrInfo : InstrInfo {}
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
def AMDILAsmWriter : AsmWriter {
string AsmWriterClassName = "AsmPrinter";
def AMDGPUAsmWriter : AsmWriter {
string AsmWriterClassName = "InstPrinter";
int Variant = 0;
bit isMCAsmWriter = 1;
}
def AMDILAsmParser : AsmParser {
@ -105,9 +106,9 @@ def AMDILAsmParser : AsmParser {
}
def AMDIL : Target {
def AMDGPU : Target {
// Pull in Instruction Info:
let InstructionSet = AMDILInstrInfo;
let AssemblyWriters = [AMDILAsmWriter];
let AssemblyWriters = [AMDGPUAsmWriter];
let AssemblyParsers = [AMDILAsmParser];
}

2
src/gallium/drivers/radeon/AMDILInstrInfo.cpp
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@ -27,7 +27,7 @@
using namespace llvm;
AMDILInstrInfo::AMDILInstrInfo(TargetMachine &tm)
: AMDILGenInstrInfo(),
: AMDGPUGenInstrInfo(),
RI(tm, *this),
TM(tm) {
}

2
src/gallium/drivers/radeon/AMDILInstrInfo.h
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@ -25,7 +25,7 @@ namespace llvm {
// instruction info tracks.
//
//class AMDILTargetMachine;
class AMDILInstrInfo : public AMDILGenInstrInfo {
class AMDILInstrInfo : public AMDGPUGenInstrInfo {
private:
const AMDILRegisterInfo RI;
TargetMachine &TM;

2
src/gallium/drivers/radeon/AMDILRegisterInfo.cpp
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@ -29,7 +29,7 @@ using namespace llvm;
AMDILRegisterInfo::AMDILRegisterInfo(TargetMachine &tm,
const TargetInstrInfo &tii)
: AMDILGenRegisterInfo(0), // RA???
: AMDGPUGenRegisterInfo(0), // RA???
TM(tm), TII(tii)
{
baseOffset = 0;

2
src/gallium/drivers/radeon/AMDILRegisterInfo.h
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@ -34,7 +34,7 @@ namespace llvm
};
}
struct AMDILRegisterInfo : public AMDILGenRegisterInfo
struct AMDILRegisterInfo : public AMDGPUGenRegisterInfo
{
TargetMachine &TM;
const TargetInstrInfo &TII;

71
src/gallium/drivers/radeon/AMDILSubtarget.cpp
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@ -16,85 +16,16 @@
#include "AMDILDevices.h"
#include "AMDILUtilityFunctions.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/MC/SubtargetFeature.h"
using namespace llvm;
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_TARGET_DESC
#include "AMDGPUGenSubtargetInfo.inc"
AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT, llvm::StringRef CPU, llvm::StringRef FS) : AMDILGenSubtargetInfo( TT, CPU, FS ),
AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT, llvm::StringRef CPU, llvm::StringRef FS) : AMDGPUGenSubtargetInfo( TT, CPU, FS ),
mDumpCode(false)
{
memset(CapsOverride, 0, sizeof(*CapsOverride)
* AMDILDeviceInfo::MaxNumberCapabilities);
// Default card
std::string GPU = "rv770";
GPU = CPU;
mIs64bit = false;
mVersion = 0;
SmallVector<StringRef, DEFAULT_VEC_SLOTS> Features;
SplitString(FS, Features, ",");
mDefaultSize[0] = 64;
mDefaultSize[1] = 1;
mDefaultSize[2] = 1;
std::string newFeatures = "";
#if defined(_DEBUG) || defined(DEBUG)
bool useTest = false;
#endif
for (size_t x = 0; x < Features.size(); ++x) {
if (Features[x].startswith("+mwgs")) {
SmallVector<StringRef, DEFAULT_VEC_SLOTS> sizes;
SplitString(Features[x], sizes, "-");
size_t mDim = ::atoi(sizes[1].data());
if (mDim > 3) {
mDim = 3;
}
for (size_t y = 0; y < mDim; ++y) {
mDefaultSize[y] = ::atoi(sizes[y+2].data());
}
#if defined(_DEBUG) || defined(DEBUG)
} else if (!Features[x].compare("test")) {
useTest = true;
#endif
} else if (Features[x].startswith("+cal")) {
SmallVector<StringRef, DEFAULT_VEC_SLOTS> version;
SplitString(Features[x], version, "=");
mVersion = ::atoi(version[1].data());
} else {
GPU = CPU;
if (x > 0) newFeatures += ',';
newFeatures += Features[x];
}
}
// If we don't have a version then set it to
// -1 which enables everything. This is for
// offline devices.
if (!mVersion) {
mVersion = (uint32_t)-1;
}
for (int x = 0; x < 3; ++x) {
if (!mDefaultSize[x]) {
mDefaultSize[x] = 1;
}
}
#if defined(_DEBUG) || defined(DEBUG)
if (useTest) {
GPU = "kauai";
}
#endif
ParseSubtargetFeatures(GPU, newFeatures);
#if defined(_DEBUG) || defined(DEBUG)
if (useTest) {
GPU = "test";
}
#endif
mDevName = GPU;
mDevice = AMDILDeviceInfo::getDeviceFromName(mDevName, this, mIs64bit);
}
AMDILSubtarget::~AMDILSubtarget()
{

8
src/gallium/drivers/radeon/AMDILSubtarget.h
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@ -30,8 +30,8 @@ namespace llvm {
class AMDILKernelManager;
class AMDILGlobalManager;
class AMDILDevice;
class AMDILSubtarget : public AMDILGenSubtargetInfo {
private:
class AMDILSubtarget : public AMDGPUGenSubtargetInfo {
protected:
bool CapsOverride[AMDILDeviceInfo::MaxNumberCapabilities];
mutable AMDILGlobalManager *mGM;
mutable AMDILKernelManager *mKM;
@ -64,10 +64,10 @@ namespace llvm {
// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options. Definition of function is
//auto generated by tblgen.
void
virtual void
ParseSubtargetFeatures(
llvm::StringRef CPU,
llvm::StringRef FS);
llvm::StringRef FS) { assert(!"Unimplemented"); }
bool dumpCode() const { return mDumpCode; }
};

22
src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.cpp
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@ -19,26 +19,26 @@
using namespace llvm;
static MCInstrInfo *createAMDILMCInstrInfo() {
static MCInstrInfo *createAMDGPUMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
InitAMDILMCInstrInfo(X);
InitAMDGPUMCInstrInfo(X);
return X;
}
static MCRegisterInfo *createAMDILMCRegisterInfo(StringRef TT) {
static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitAMDILMCRegisterInfo(X, 0);
InitAMDGPUMCRegisterInfo(X, 0);
return X;
}
static MCSubtargetInfo *createAMDILMCSubtargetInfo(StringRef TT, StringRef CPU,
static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo * X = new MCSubtargetInfo();
InitAMDILMCSubtargetInfo(X, TT, CPU, FS);
InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
static MCCodeGenInfo *createAMDILMCCodeGenInfo(StringRef TT, Reloc::Model RM,
static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
@ -50,12 +50,12 @@ extern "C" void LLVMInitializeAMDGPUTargetMC() {
RegisterMCAsmInfo<AMDILMCAsmInfo> Y(TheAMDGPUTarget);
TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDILMCCodeGenInfo);
TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo);
TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDILMCInstrInfo);
TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo);
TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDILMCRegisterInfo);
TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo);
TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDILMCSubtargetInfo);
TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo);
}

1
src/gallium/drivers/radeon/Makefile.sources
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@ -31,6 +31,7 @@ CPP_SOURCES := \
AMDILRegisterInfo.cpp \
AMDILSIDevice.cpp \
AMDILSubtarget.cpp \
AMDGPUSubtarget.cpp \
AMDGPUTargetMachine.cpp \
AMDGPUISelLowering.cpp \
AMDGPUConvertToISA.cpp \

4
src/gallium/drivers/radeon/R600CodeEmitter.cpp
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@ -17,8 +17,8 @@
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "AMDGPUCodeEmitter.h"
#include "AMDGPUUtil.h"
#include "AMDILCodeEmitter.h"
#include "AMDILInstrInfo.h"
#include "AMDILUtilityFunctions.h"
#include "R600InstrInfo.h"
@ -39,7 +39,7 @@ using namespace llvm;
namespace {
class R600CodeEmitter : public MachineFunctionPass, public AMDILCodeEmitter {
class R600CodeEmitter : public MachineFunctionPass, public AMDGPUCodeEmitter {
private:

4
src/gallium/drivers/radeon/SICodeEmitter.cpp
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@ -14,8 +14,8 @@
#include "AMDGPU.h"
#include "AMDGPUCodeEmitter.h"
#include "AMDGPUUtil.h"
#include "AMDILCodeEmitter.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@ -32,7 +32,7 @@ using namespace llvm;
namespace {
class SICodeEmitter : public MachineFunctionPass, public AMDILCodeEmitter {
class SICodeEmitter : public MachineFunctionPass, public AMDGPUCodeEmitter {
private:
static char ID;