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aco: fix non-rtz pack_half_2x16 

We were using the wrong conversion opcode. The high bits are also not
zero'd on GFX10, which can cause v_cvt_pk_u16_u32 to clamp.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: df645fa369 ('aco: implement VK_KHR_shader_float_controls')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6346>
This commit is contained in:
Rhys Perry 2020-08-17 11:28:07 +01:00 committed by Marge Bot
parent e802bff69e
commit 9c1e0d86a8
1 changed files with 11 additions and 5 deletions
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16
src/amd/compiler/aco_instruction_selection.cpp
View File

@ -2714,12 +2714,18 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
Temp src0 = bld.tmp(v1);
Temp src1 = bld.tmp(v1);
bld.pseudo(aco_opcode::p_split_vector, Definition(src0), Definition(src1), src);
if (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)
if (0 && (!ctx->block->fp_mode.care_about_round32 || ctx->block->fp_mode.round32 == fp_round_tz)) {
bld.vop3(aco_opcode::v_cvt_pkrtz_f16_f32, Definition(dst), src0, src1);
else
bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst),
bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src0),
bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), src1));
} else {
src0 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src0);
src1 = bld.vop1(aco_opcode::v_cvt_f16_f32, bld.def(v1), src1);
if (ctx->program->chip_class >= GFX10) {
/* the high bits of v_cvt_f16_f32 isn't zero'd on GFX10 */
bld.vop3(aco_opcode::v_pack_b32_f16, Definition(dst), src0, src1);
} else {
bld.vop3(aco_opcode::v_cvt_pk_u16_u32, Definition(dst), src0, src1);
}
}
} else {
isel_err(&instr->instr, "Unimplemented NIR instr bit size");
}