intel/fs: fix metadata preserve on trace_ray intrinsic
c78be5da30("intel/fs: lower ray query intrinsics") introduced a helper function using nir_(push|pop)_if which invalidated dominance & block_index for the replacement of nir_intrinsic_rt_trace_ray. We can still keep dominance/block_index metadata for the lowering of nir_intrinsic_rt_execute_callable though. This change uses 2 different lowering function with correct metadata preservation. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes:c78be5da30("intel/fs: lower ray query intrinsics") Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15910>
This commit is contained in:
Lionel Landwerlin
Marge Bot
parent
fcd6b2a47a
commit
9c0805ef91
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@ -125,7 +125,7 @@ store_resume_addr(nir_builder *b, nir_intrinsic_instr *call)
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}
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static bool
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lower_shader_calls_instr(struct nir_builder *b, nir_instr *instr, void *data)
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lower_shader_trace_ray_instr(struct nir_builder *b, nir_instr *instr, void *data)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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@ -134,117 +134,130 @@ lower_shader_calls_instr(struct nir_builder *b, nir_instr *instr, void *data)
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* brw_nir_lower_rt_intrinsics()
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*/
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nir_intrinsic_instr *call = nir_instr_as_intrinsic(instr);
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switch (call->intrinsic) {
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case nir_intrinsic_rt_trace_ray: {
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b->cursor = nir_instr_remove(instr);
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store_resume_addr(b, call);
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nir_ssa_def *as_addr = call->src[0].ssa;
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nir_ssa_def *ray_flags = call->src[1].ssa;
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/* From the SPIR-V spec:
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*
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* "Only the 8 least-significant bits of Cull Mask are used by this
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* instruction - other bits are ignored.
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*
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* Only the 4 least-significant bits of SBT Offset and SBT Stride are
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* used by this instruction - other bits are ignored.
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*
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* Only the 16 least-significant bits of Miss Index are used by this
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* instruction - other bits are ignored."
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*/
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nir_ssa_def *cull_mask = nir_iand_imm(b, call->src[2].ssa, 0xff);
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nir_ssa_def *sbt_offset = nir_iand_imm(b, call->src[3].ssa, 0xf);
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nir_ssa_def *sbt_stride = nir_iand_imm(b, call->src[4].ssa, 0xf);
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nir_ssa_def *miss_index = nir_iand_imm(b, call->src[5].ssa, 0xffff);
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nir_ssa_def *ray_orig = call->src[6].ssa;
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nir_ssa_def *ray_t_min = call->src[7].ssa;
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nir_ssa_def *ray_dir = call->src[8].ssa;
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nir_ssa_def *ray_t_max = call->src[9].ssa;
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nir_ssa_def *root_node_ptr =
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brw_nir_rt_acceleration_structure_to_root_node(b, as_addr);
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/* The hardware packet requires an address to the first element of the
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* hit SBT.
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*
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* In order to calculate this, we must multiply the "SBT Offset"
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* provided to OpTraceRay by the SBT stride provided for the hit SBT in
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* the call to vkCmdTraceRay() and add that to the base address of the
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* hit SBT. This stride is not to be confused with the "SBT Stride"
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* provided to OpTraceRay which is in units of this stride. It's a
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* rather terrible overload of the word "stride". The hardware docs
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* calls the SPIR-V stride value the "shader index multiplier" which is
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* a much more sane name.
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*/
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nir_ssa_def *hit_sbt_stride_B =
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nir_load_ray_hit_sbt_stride_intel(b);
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nir_ssa_def *hit_sbt_offset_B =
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nir_umul_32x16(b, sbt_offset, nir_u2u32(b, hit_sbt_stride_B));
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nir_ssa_def *hit_sbt_addr =
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nir_iadd(b, nir_load_ray_hit_sbt_addr_intel(b),
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nir_u2u64(b, hit_sbt_offset_B));
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/* The hardware packet takes an address to the miss BSR. */
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nir_ssa_def *miss_sbt_stride_B =
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nir_load_ray_miss_sbt_stride_intel(b);
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nir_ssa_def *miss_sbt_offset_B =
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nir_umul_32x16(b, miss_index, nir_u2u32(b, miss_sbt_stride_B));
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nir_ssa_def *miss_sbt_addr =
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nir_iadd(b, nir_load_ray_miss_sbt_addr_intel(b),
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nir_u2u64(b, miss_sbt_offset_B));
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struct brw_nir_rt_mem_ray_defs ray_defs = {
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.root_node_ptr = root_node_ptr,
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.ray_flags = nir_u2u16(b, ray_flags),
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.ray_mask = cull_mask,
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.hit_group_sr_base_ptr = hit_sbt_addr,
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.hit_group_sr_stride = nir_u2u16(b, hit_sbt_stride_B),
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.miss_sr_ptr = miss_sbt_addr,
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.orig = ray_orig,
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.t_near = ray_t_min,
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.dir = ray_dir,
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.t_far = ray_t_max,
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.shader_index_multiplier = sbt_stride,
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};
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brw_nir_rt_store_mem_ray(b, &ray_defs, BRW_RT_BVH_LEVEL_WORLD);
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nir_trace_ray_intel(b,
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nir_load_btd_global_arg_addr_intel(b),
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nir_imm_int(b, BRW_RT_BVH_LEVEL_WORLD),
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nir_imm_int(b, GEN_RT_TRACE_RAY_INITAL),
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.synchronous = false);
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return true;
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}
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case nir_intrinsic_rt_execute_callable: {
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b->cursor = nir_instr_remove(instr);
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store_resume_addr(b, call);
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nir_ssa_def *sbt_offset32 =
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nir_imul(b, call->src[0].ssa,
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nir_u2u32(b, nir_load_callable_sbt_stride_intel(b)));
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nir_ssa_def *sbt_addr =
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nir_iadd(b, nir_load_callable_sbt_addr_intel(b),
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nir_u2u64(b, sbt_offset32));
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brw_nir_btd_spawn(b, sbt_addr);
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return true;
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}
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default:
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if (call->intrinsic != nir_intrinsic_rt_trace_ray)
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return false;
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}
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b->cursor = nir_instr_remove(instr);
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store_resume_addr(b, call);
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nir_ssa_def *as_addr = call->src[0].ssa;
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nir_ssa_def *ray_flags = call->src[1].ssa;
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/* From the SPIR-V spec:
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*
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* "Only the 8 least-significant bits of Cull Mask are used by this
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* instruction - other bits are ignored.
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*
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* Only the 4 least-significant bits of SBT Offset and SBT Stride are
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* used by this instruction - other bits are ignored.
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*
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* Only the 16 least-significant bits of Miss Index are used by this
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* instruction - other bits are ignored."
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*/
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nir_ssa_def *cull_mask = nir_iand_imm(b, call->src[2].ssa, 0xff);
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nir_ssa_def *sbt_offset = nir_iand_imm(b, call->src[3].ssa, 0xf);
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nir_ssa_def *sbt_stride = nir_iand_imm(b, call->src[4].ssa, 0xf);
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nir_ssa_def *miss_index = nir_iand_imm(b, call->src[5].ssa, 0xffff);
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nir_ssa_def *ray_orig = call->src[6].ssa;
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nir_ssa_def *ray_t_min = call->src[7].ssa;
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nir_ssa_def *ray_dir = call->src[8].ssa;
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nir_ssa_def *ray_t_max = call->src[9].ssa;
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nir_ssa_def *root_node_ptr =
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brw_nir_rt_acceleration_structure_to_root_node(b, as_addr);
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/* The hardware packet requires an address to the first element of the
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* hit SBT.
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*
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* In order to calculate this, we must multiply the "SBT Offset"
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* provided to OpTraceRay by the SBT stride provided for the hit SBT in
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* the call to vkCmdTraceRay() and add that to the base address of the
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* hit SBT. This stride is not to be confused with the "SBT Stride"
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* provided to OpTraceRay which is in units of this stride. It's a
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* rather terrible overload of the word "stride". The hardware docs
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* calls the SPIR-V stride value the "shader index multiplier" which is
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* a much more sane name.
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*/
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nir_ssa_def *hit_sbt_stride_B =
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nir_load_ray_hit_sbt_stride_intel(b);
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nir_ssa_def *hit_sbt_offset_B =
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nir_umul_32x16(b, sbt_offset, nir_u2u32(b, hit_sbt_stride_B));
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nir_ssa_def *hit_sbt_addr =
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nir_iadd(b, nir_load_ray_hit_sbt_addr_intel(b),
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nir_u2u64(b, hit_sbt_offset_B));
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/* The hardware packet takes an address to the miss BSR. */
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nir_ssa_def *miss_sbt_stride_B =
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nir_load_ray_miss_sbt_stride_intel(b);
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nir_ssa_def *miss_sbt_offset_B =
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nir_umul_32x16(b, miss_index, nir_u2u32(b, miss_sbt_stride_B));
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nir_ssa_def *miss_sbt_addr =
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nir_iadd(b, nir_load_ray_miss_sbt_addr_intel(b),
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nir_u2u64(b, miss_sbt_offset_B));
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struct brw_nir_rt_mem_ray_defs ray_defs = {
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.root_node_ptr = root_node_ptr,
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.ray_flags = nir_u2u16(b, ray_flags),
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.ray_mask = cull_mask,
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.hit_group_sr_base_ptr = hit_sbt_addr,
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.hit_group_sr_stride = nir_u2u16(b, hit_sbt_stride_B),
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.miss_sr_ptr = miss_sbt_addr,
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.orig = ray_orig,
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.t_near = ray_t_min,
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.dir = ray_dir,
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.t_far = ray_t_max,
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.shader_index_multiplier = sbt_stride,
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};
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brw_nir_rt_store_mem_ray(b, &ray_defs, BRW_RT_BVH_LEVEL_WORLD);
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nir_trace_ray_intel(b,
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nir_load_btd_global_arg_addr_intel(b),
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nir_imm_int(b, BRW_RT_BVH_LEVEL_WORLD),
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nir_imm_int(b, GEN_RT_TRACE_RAY_INITAL),
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.synchronous = false);
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return true;
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}
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static bool
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lower_shader_call_instr(struct nir_builder *b, nir_instr *instr, void *data)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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/* Leave nir_intrinsic_rt_resume to be lowered by
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* brw_nir_lower_rt_intrinsics()
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*/
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nir_intrinsic_instr *call = nir_instr_as_intrinsic(instr);
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if (call->intrinsic != nir_intrinsic_rt_execute_callable)
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return false;
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b->cursor = nir_instr_remove(instr);
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store_resume_addr(b, call);
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nir_ssa_def *sbt_offset32 =
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nir_imul(b, call->src[0].ssa,
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nir_u2u32(b, nir_load_callable_sbt_stride_intel(b)));
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nir_ssa_def *sbt_addr =
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nir_iadd(b, nir_load_callable_sbt_addr_intel(b),
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nir_u2u64(b, sbt_offset32));
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brw_nir_btd_spawn(b, sbt_addr);
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return true;
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}
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bool
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brw_nir_lower_shader_calls(nir_shader *shader)
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{
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return nir_shader_instructions_pass(shader,
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lower_shader_calls_instr,
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nir_metadata_block_index |
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nir_metadata_dominance,
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NULL);
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return
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nir_shader_instructions_pass(shader,
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lower_shader_trace_ray_instr,
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nir_metadata_none,
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NULL) |
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nir_shader_instructions_pass(shader,
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lower_shader_call_instr,
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nir_metadata_block_index |
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nir_metadata_dominance,
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NULL);
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}
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/** Creates a trivial return shader
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