aco: use io semantics to get an intrinsic's slot
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6689>
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@ -4096,14 +4096,13 @@ std::pair<Temp, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context *ctx
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return offs;
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}
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bool tcs_driver_location_matches_api_mask(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex, uint64_t mask, bool *indirect)
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bool tcs_compare_intrin_with_mask(isel_context *ctx, nir_intrinsic_instr *instr, bool per_vertex, uint64_t mask, bool *indirect)
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{
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assert(per_vertex || ctx->shader->info.stage == MESA_SHADER_TESS_CTRL);
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if (mask == 0)
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return false;
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unsigned drv_loc = nir_intrinsic_base(instr);
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nir_src *off_src = nir_get_io_offset_src(instr);
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if (!nir_src_is_const(*off_src)) {
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@ -4112,9 +4111,10 @@ bool tcs_driver_location_matches_api_mask(isel_context *ctx, nir_intrinsic_instr
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}
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*indirect = false;
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uint64_t slot = per_vertex
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? ctx->output_drv_loc_to_var_slot[ctx->shader->info.stage][drv_loc / 4]
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: (ctx->output_tcs_patch_drv_loc_to_var_slot[drv_loc / 4] - VARYING_SLOT_PATCH0);
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uint64_t slot = nir_intrinsic_io_semantics(instr).location;
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if (!per_vertex)
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slot -= VARYING_SLOT_PATCH0;
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return (((uint64_t) 1) << slot) & mask;
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}
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@ -4179,7 +4179,7 @@ void visit_store_ls_or_es_output(isel_context *ctx, nir_intrinsic_instr *instr)
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if (ctx->tcs_in_out_eq && store_output_to_temps(ctx, instr)) {
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/* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
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bool indirect_write;
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bool temp_only_input = tcs_driver_location_matches_api_mask(ctx, instr, true, ctx->tcs_temp_only_inputs, &indirect_write);
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bool temp_only_input = tcs_compare_intrin_with_mask(ctx, instr, true, ctx->tcs_temp_only_inputs, &indirect_write);
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if (temp_only_input && !indirect_write)
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return;
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}
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@ -4230,7 +4230,7 @@ bool tcs_output_is_read_by_tes(isel_context *ctx, nir_intrinsic_instr *instr, bo
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: ctx->program->info->tcs.tes_patch_inputs_read;
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bool indirect_write = false;
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bool output_read_by_tes = tcs_driver_location_matches_api_mask(ctx, instr, per_vertex, mask, &indirect_write);
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bool output_read_by_tes = tcs_compare_intrin_with_mask(ctx, instr, per_vertex, mask, &indirect_write);
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return indirect_write || output_read_by_tes;
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}
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@ -4241,7 +4241,7 @@ bool tcs_output_is_read_by_tcs(isel_context *ctx, nir_intrinsic_instr *instr, bo
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: ctx->shader->info.patch_outputs_read;
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bool indirect_write = false;
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bool output_read = tcs_driver_location_matches_api_mask(ctx, instr, per_vertex, mask, &indirect_write);
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bool output_read = tcs_compare_intrin_with_mask(ctx, instr, per_vertex, mask, &indirect_write);
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return indirect_write || output_read;
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}
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@ -113,8 +113,6 @@ struct isel_context {
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/* I/O information */
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shader_io_state inputs;
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shader_io_state outputs;
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uint8_t output_drv_loc_to_var_slot[MESA_SHADER_COMPUTE][VARYING_SLOT_MAX];
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uint8_t output_tcs_patch_drv_loc_to_var_slot[VARYING_SLOT_MAX];
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};
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inline Temp get_arg(isel_context *ctx, struct ac_arg arg)
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@ -478,9 +478,6 @@ setup_vs_variables(isel_context *ctx, nir_shader *nir)
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{
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if (ctx->stage == vertex_vs || ctx->stage == ngg_vertex_gs)
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variable->data.driver_location = variable->data.location * 4;
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assert(variable->data.location >= 0 && variable->data.location <= UINT8_MAX);
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ctx->output_drv_loc_to_var_slot[MESA_SHADER_VERTEX][variable->data.driver_location / 4] = variable->data.location;
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}
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if (ctx->stage == vertex_vs || ctx->stage == ngg_vertex_gs) {
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@ -565,19 +562,6 @@ setup_tcs_info(isel_context *ctx, nir_shader *nir, nir_shader *vs)
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ctx->program->lds_alloc_granule;
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}
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void
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setup_tcs_variables(isel_context *ctx, nir_shader *nir)
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{
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nir_foreach_shader_out_variable(variable, nir) {
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assert(variable->data.location >= 0 && variable->data.location <= UINT8_MAX);
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if (variable->data.patch)
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ctx->output_tcs_patch_drv_loc_to_var_slot[variable->data.driver_location / 4] = variable->data.location;
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else
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ctx->output_drv_loc_to_var_slot[MESA_SHADER_TESS_CTRL][variable->data.driver_location / 4] = variable->data.location;
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}
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}
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void
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setup_tes_variables(isel_context *ctx, nir_shader *nir)
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{
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@ -622,7 +606,6 @@ setup_variables(isel_context *ctx, nir_shader *nir)
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break;
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}
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case MESA_SHADER_TESS_CTRL: {
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setup_tcs_variables(ctx, nir);
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break;
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}
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case MESA_SHADER_TESS_EVAL: {
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