radeonsi/gfx10: enable LATE_ALLOC_GS
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Acked-by: Dave Airlie <airlied@redhat.com>
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@ -5493,9 +5493,6 @@ static void si_init_config(struct si_context *sctx)
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/* Logical CUs 16 - 31 */
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si_pm4_set_reg(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
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S_00B404_CU_EN(0xffff));
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si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
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S_00B204_CU_EN(0xffff) |
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S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
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si_pm4_set_reg(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
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S_00B104_CU_EN(0xffff));
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si_pm4_set_reg(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
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@ -5521,8 +5518,6 @@ static void si_init_config(struct si_context *sctx)
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S_028A44_ES_VERTS_PER_SUBGRP(64) |
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S_028A44_GS_PRIMS_PER_SUBGRP(4));
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}
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si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
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S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
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/* Compute LATE_ALLOC_VS.LIMIT. */
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unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
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@ -5546,13 +5541,35 @@ static void si_init_config(struct si_context *sctx)
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late_alloc_limit = (num_cu_per_sh - 2) * 4;
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}
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unsigned cu_mask_vs = 0xffff;
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unsigned cu_mask_gs = 0xffff;
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if (late_alloc_limit > 2) {
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if (sctx->chip_class >= GFX10) {
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/* CU2 & CU3 disabled because of the dual CU design */
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cu_mask_vs = 0xfff3;
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cu_mask_gs = 0xfff3; /* NGG only */
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} else {
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cu_mask_vs = 0xfffe; /* 1 CU disabled */
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}
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}
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/* VS can't execute on one CU if the limit is > 2. */
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si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
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S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
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S_00B118_CU_EN(cu_mask_vs) |
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S_00B118_WAVE_LIMIT(0x3F));
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si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
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S_00B11C_LIMIT(late_alloc_limit));
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si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
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S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
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if (sctx->chip_class >= GFX10) {
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si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
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S_00B204_CU_EN(0xffff) |
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S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit));
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}
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si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
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S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
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}
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