pan/bi: Support dual texture scheduling

Teach the scheduler about dual texturing to avoid an artifical "must not
last" constraint causing suboptimal scheduling like

clause_1:
ds(0) nbb tex ncph dwb(0)
{
    *NOP t0
    +TEXC.skip t1, r0, r1, 0xf1e00144, @r4
    *NOP t0
    +NOP t1
}

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13723>
This commit is contained in:
Alyssa Rosenzweig 2021-11-08 14:10:48 -05:00 committed by Marge Bot
parent 98c1b3e7e1
commit 9b2a383af8
1 changed files with 6 additions and 1 deletions

View File

@ -524,12 +524,17 @@ bi_can_add(bi_instr *ins)
* pseudoinstructions writing multiple destinations (expanding to multiple
* paired instructions) can run afoul of the "no two writes on the last clause"
* constraint, so we check for that here.
*
* Exception to the exception: TEXC, which writes to multiple sets of staging
* registers. Staging registers bypass the usual register write mechanism so
* this restriction does not apply.
*/
static bool
bi_must_not_last(bi_instr *ins)
{
return !bi_is_null(ins->dest[0]) && !bi_is_null(ins->dest[1]);
return !bi_is_null(ins->dest[0]) && !bi_is_null(ins->dest[1]) &&
(ins->op != BI_OPCODE_TEXC);
}
/* Check for a message-passing instruction. +DISCARD.f32 is special-cased; we