From 9b20120d57f7514f7072e95452534380b26a8ce2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 14 May 2022 05:55:29 -0400 Subject: [PATCH] radeonsi/gfx11: fix VM faults due to the attribute ring Reviewed-by: Mihai Preda Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_pipe.c | 3 +-- src/gallium/drivers/radeonsi/si_state.c | 13 +++++-------- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 13b94df218e..383056f03fe 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -1387,8 +1387,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws, SI_RESOURCE_FLAG_DRIVER_INTERNAL | SI_RESOURCE_FLAG_DISCARDABLE, PIPE_USAGE_DEFAULT, - /* TODO: remove the overallocation */ - attr_ring_size * 16, 2 * 1024 * 1024); + attr_ring_size, 2 * 1024 * 1024); } /* Create the auxiliary context. This must be done last. */ diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 015cb277895..aea74b7f1e9 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -5883,14 +5883,11 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing) S_028620_VERTEX_RATE(2) | S_028620_PRIM_RATE(1)); /* We must wait for idle before changing the SPI attribute ring registers. */ - si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); - si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); - - si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); - si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); - - si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); - si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); + /* TODO: Find a more reliable way to wait for idle. */ + for (unsigned i = 0; i < 4; i++) { + si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); + si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); + } si_pm4_set_reg(pm4, R_031110_SPI_GS_THROTTLE_CNTL1, 0x12355123); si_pm4_set_reg(pm4, R_031114_SPI_GS_THROTTLE_CNTL2, 0x1544D);