i965/nir/vec4: Implement multiplication
Implementation based on the vec4_visitor IR implementation for the operations ir_binop_mul and ir_binop_imul_high. Adds NIR ALU operations: * nir_op_fmul * nir_op_imul * nir_op_imul_high * nir_op_umul_high Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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@ -700,6 +700,50 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
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inst->saturate = instr->dest.saturate;
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break;
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case nir_op_fmul:
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inst = emit(MUL(dst, op[0], op[1]));
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inst->saturate = instr->dest.saturate;
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break;
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case nir_op_imul: {
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nir_const_value *value0 = nir_src_as_const_value(instr->src[0].src);
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nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
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/* For integer multiplication, the MUL uses the low 16 bits of one of
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* the operands (src0 through SNB, src1 on IVB and later). The MACH
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* accumulates in the contribution of the upper 16 bits of that
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* operand. If we can determine that one of the args is in the low
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* 16 bits, though, we can just emit a single MUL.
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*/
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if (value0 && value0->u[0] < (1 << 16)) {
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if (devinfo->gen < 7)
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emit(MUL(dst, op[0], op[1]));
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else
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emit(MUL(dst, op[1], op[0]));
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} else if (value1 && value1->u[0] < (1 << 16)) {
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if (devinfo->gen < 7)
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emit(MUL(dst, op[1], op[0]));
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else
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emit(MUL(dst, op[0], op[1]));
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} else {
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struct brw_reg acc = retype(brw_acc_reg(8), dst.type);
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emit(MUL(acc, op[0], op[1]));
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emit(MACH(dst_null_d(), op[0], op[1]));
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emit(MOV(dst, src_reg(acc)));
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}
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break;
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}
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case nir_op_imul_high:
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case nir_op_umul_high: {
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struct brw_reg acc = retype(brw_acc_reg(8), dst.type);
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emit(MUL(acc, op[0], op[1]));
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emit(MACH(dst, op[0], op[1]));
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break;
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}
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default:
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unreachable("Unimplemented ALU operation");
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}
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