anv/query: flush render target before copying results
This change tracks render target writes in the pipeline and applies a
render target flush before copying the query results to make sure the
preceding operations have landed in memory before the command streamer
initiates the copy.
v2: Simplify logic in CopyQueryResults (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108909
Fixes: 37f9788e9a
("anv: flush pipeline before query result copies")
Cc: mesa-stable@lists.freedesktop.org
This commit is contained in:
parent
c1b6cb068c
commit
9a7b319903
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@ -1747,6 +1747,13 @@ enum anv_pipe_bits {
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* we would have to CS stall on every flush which could be bad.
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*/
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ANV_PIPE_NEEDS_CS_STALL_BIT = (1 << 21),
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/* This bit does not exist directly in PIPE_CONTROL. It means that render
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* target operations are ongoing. Some operations like copies on the
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* command streamer might need to be aware of this to trigger the
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* appropriate stall before they can proceed with the copy.
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*/
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ANV_PIPE_RENDER_TARGET_WRITES = (1 << 22),
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};
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#define ANV_PIPE_FLUSH_BITS ( \
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@ -263,4 +263,5 @@ genX(blorp_exec)(struct blorp_batch *batch,
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cmd_buffer->state.gfx.vb_dirty = ~0;
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cmd_buffer->state.gfx.dirty = ~0;
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cmd_buffer->state.push_constants_dirty = ~0;
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
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}
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@ -1766,6 +1766,12 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
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pipe.StallAtPixelScoreboard = true;
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}
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/* If a render target flush was emitted, then we can toggle off the bit
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* saying that render target writes are ongoing.
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*/
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if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
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bits &= ~(ANV_PIPE_RENDER_TARGET_WRITES);
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bits &= ~(ANV_PIPE_FLUSH_BITS | ANV_PIPE_CS_STALL_BIT);
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}
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@ -2777,6 +2783,8 @@ void genX(CmdDraw)(
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prim.StartInstanceLocation = firstInstance;
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prim.BaseVertexLocation = 0;
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}
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
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}
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void genX(CmdDrawIndexed)(
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@ -2816,6 +2824,8 @@ void genX(CmdDrawIndexed)(
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prim.StartInstanceLocation = firstInstance;
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prim.BaseVertexLocation = vertexOffset;
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}
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
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}
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/* Auto-Draw / Indirect Registers */
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@ -2949,6 +2959,8 @@ void genX(CmdDrawIndirect)(
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offset += stride;
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}
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
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}
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void genX(CmdDrawIndexedIndirect)(
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@ -2988,6 +3000,8 @@ void genX(CmdDrawIndexedIndirect)(
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offset += stride;
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}
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
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}
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static VkResult
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@ -302,4 +302,5 @@ genX(cmd_buffer_so_memcpy)(struct anv_cmd_buffer *cmd_buffer,
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}
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cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES;
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}
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@ -729,6 +729,15 @@ void genX(CmdCopyQueryPoolResults)(
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ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
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ANV_FROM_HANDLE(anv_buffer, buffer, destBuffer);
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/* If render target writes are ongoing, request a render target cache flush
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* to ensure proper ordering of the commands from the 3d pipe and the
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* command streamer.
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*/
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if (cmd_buffer->state.pending_pipe_bits & ANV_PIPE_RENDER_TARGET_WRITES) {
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cmd_buffer->state.pending_pipe_bits |=
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ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
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}
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if ((flags & VK_QUERY_RESULT_WAIT_BIT) ||
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(cmd_buffer->state.pending_pipe_bits & ANV_PIPE_FLUSH_BITS)) {
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cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
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