ac/surface: expose all 64K_R_X and 256K_R_X modifiers on gfx11
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17410>
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@ -405,48 +405,56 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
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unsigned num_pipes = 1 << pipe_xor_bits;
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/* R_X swizzle modes are the best for rendering and DCC requires them. */
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unsigned swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X :
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AMD_FMT_MOD_TILE_GFX9_64K_R_X;
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uint64_t modifier_r_x = AMD_FMT_MOD |
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AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
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AMD_FMT_MOD_SET(TILE, swizzle_r_x) |
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AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
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AMD_FMT_MOD_SET(PACKERS, pkrs);
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for (unsigned i = 0; i < 2; i++) {
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unsigned swizzle_r_x;
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/* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */
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uint64_t modifier_dcc_best = modifier_r_x |
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AMD_FMT_MOD_SET(DCC, 1) |
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AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) |
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AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
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AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B);
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/* Insert the best one first. */
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if (num_pipes > 16)
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swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX11_256K_R_X : AMD_FMT_MOD_TILE_GFX9_64K_R_X;
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else
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swizzle_r_x = !i ? AMD_FMT_MOD_TILE_GFX9_64K_R_X : AMD_FMT_MOD_TILE_GFX11_256K_R_X;
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/* DCC settings for 4K and greater resolutions. (required by display hw) */
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uint64_t modifier_dcc_4k = modifier_r_x |
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AMD_FMT_MOD_SET(DCC, 1) |
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AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
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AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
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AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
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uint64_t modifier_r_x = AMD_FMT_MOD |
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AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
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AMD_FMT_MOD_SET(TILE, swizzle_r_x) |
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AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
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AMD_FMT_MOD_SET(PACKERS, pkrs);
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/* Modifiers have to be sorted from best to worst.
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*
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* Top level order:
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* 1. The best chip-specific modifiers with DCC, potentially non-displayable.
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* 2. Chip-specific displayable modifiers with DCC.
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* 3. Chip-specific displayable modifiers without DCC.
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* 4. Chip-independent modifiers without DCC.
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* 5. Linear.
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*/
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/* DCC_CONSTANT_ENCODE is not set because it can't vary with gfx11 (it's implied to be 1). */
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uint64_t modifier_dcc_best = modifier_r_x |
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AMD_FMT_MOD_SET(DCC, 1) |
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AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 0) |
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AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
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AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B);
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/* Add the best non-displayable modifier first. */
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ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1));
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/* DCC settings for 4K and greater resolutions. (required by display hw) */
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uint64_t modifier_dcc_4k = modifier_r_x |
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AMD_FMT_MOD_SET(DCC, 1) |
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AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
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AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
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AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B);
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/* Displayable modifiers are next. */
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/* Add other displayable DCC settings. (DCC_RETILE implies displayable on all chips) */
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ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1))
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ADD_MOD(modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1))
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/* Modifiers have to be sorted from best to worst.
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*
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* Top level order:
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* 1. The best chip-specific modifiers with DCC, potentially non-displayable.
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* 2. Chip-specific displayable modifiers with DCC.
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* 3. Chip-specific displayable modifiers without DCC.
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* 4. Chip-independent modifiers without DCC.
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* 5. Linear.
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*/
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/* Add one without DCC that is displayable (it's also optimal for non-displayable cases). */
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ADD_MOD(modifier_r_x)
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/* Add the best non-displayable modifier first. */
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ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1));
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/* Displayable modifiers are next. */
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/* Add other displayable DCC settings. (DCC_RETILE implies displayable on all chips) */
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ADD_MOD(modifier_dcc_best | AMD_FMT_MOD_SET(DCC_RETILE, 1))
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ADD_MOD(modifier_dcc_4k | AMD_FMT_MOD_SET(DCC_RETILE, 1))
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/* Add one without DCC that is displayable (it's also optimal for non-displayable cases). */
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ADD_MOD(modifier_r_x)
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}
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/* Add one that is compatible with other gfx11 chips. */
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ADD_MOD(AMD_FMT_MOD |
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