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r300/compiler: Refactor to allow different instruction types 

Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
This commit is contained in:
Nicolai Hähnle 2009-10-04 11:25:48 +02:00
parent e6b137dcce
commit 995135479d
16 changed files with 443 additions and 437 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
src/gallium/drivers/r300/r300_tgsi_to_rc.c
View File

@ -226,31 +226,31 @@ static void transform_texture(struct rc_instruction * dst, struct tgsi_instructi
{
switch(src.Texture) {
case TGSI_TEXTURE_1D:
dst->I.TexSrcTarget = RC_TEXTURE_1D;
dst->U.I.TexSrcTarget = RC_TEXTURE_1D;
break;
case TGSI_TEXTURE_2D:
dst->I.TexSrcTarget = RC_TEXTURE_2D;
dst->U.I.TexSrcTarget = RC_TEXTURE_2D;
break;
case TGSI_TEXTURE_3D:
dst->I.TexSrcTarget = RC_TEXTURE_3D;
dst->U.I.TexSrcTarget = RC_TEXTURE_3D;
break;
case TGSI_TEXTURE_CUBE:
dst->I.TexSrcTarget = RC_TEXTURE_CUBE;
dst->U.I.TexSrcTarget = RC_TEXTURE_CUBE;
break;
case TGSI_TEXTURE_RECT:
dst->I.TexSrcTarget = RC_TEXTURE_RECT;
dst->U.I.TexSrcTarget = RC_TEXTURE_RECT;
break;
case TGSI_TEXTURE_SHADOW1D:
dst->I.TexSrcTarget = RC_TEXTURE_1D;
dst->I.TexShadow = 1;
dst->U.I.TexSrcTarget = RC_TEXTURE_1D;
dst->U.I.TexShadow = 1;
break;
case TGSI_TEXTURE_SHADOW2D:
dst->I.TexSrcTarget = RC_TEXTURE_2D;
dst->I.TexShadow = 1;
dst->U.I.TexSrcTarget = RC_TEXTURE_2D;
dst->U.I.TexShadow = 1;
break;
case TGSI_TEXTURE_SHADOWRECT:
dst->I.TexSrcTarget = RC_TEXTURE_RECT;
dst->I.TexShadow = 1;
dst->U.I.TexSrcTarget = RC_TEXTURE_RECT;
dst->U.I.TexShadow = 1;
break;
}
}
@ -263,17 +263,17 @@ static void transform_instruction(struct tgsi_to_rc * ttr, struct tgsi_full_inst
struct rc_instruction * dst = rc_insert_new_instruction(ttr->compiler, ttr->compiler->Program.Instructions.Prev);
int i;
dst->I.Opcode = translate_opcode(src->Instruction.Opcode);
dst->I.SaturateMode = translate_saturate(src->Instruction.Saturate);
dst->U.I.Opcode = translate_opcode(src->Instruction.Opcode);
dst->U.I.SaturateMode = translate_saturate(src->Instruction.Saturate);
if (src->Instruction.NumDstRegs)
transform_dstreg(ttr, &dst->I.DstReg, &src->FullDstRegisters[0]);
transform_dstreg(ttr, &dst->U.I.DstReg, &src->FullDstRegisters[0]);
for(i = 0; i < src->Instruction.NumSrcRegs; ++i) {
if (src->FullSrcRegisters[i].SrcRegister.File == TGSI_FILE_SAMPLER)
dst->I.TexSrcUnit = src->FullSrcRegisters[i].SrcRegister.Index;
dst->U.I.TexSrcUnit = src->FullSrcRegisters[i].SrcRegister.Index;
else
transform_srcreg(ttr, &dst->I.SrcReg[i], &src->FullSrcRegisters[i]);
transform_srcreg(ttr, &dst->U.I.SrcReg[i], &src->FullSrcRegisters[i]);
}
/* Texturing. */

140
src/mesa/drivers/dri/r300/compiler/r300_fragprog.c
View File

@ -55,75 +55,75 @@ int r300_transform_TEX(
struct r300_fragment_program_compiler *compiler =
(struct r300_fragment_program_compiler*)data;
if (inst->I.Opcode != RC_OPCODE_TEX &&
inst->I.Opcode != RC_OPCODE_TXB &&
inst->I.Opcode != RC_OPCODE_TXP &&
inst->I.Opcode != RC_OPCODE_KIL)
if (inst->U.I.Opcode != RC_OPCODE_TEX &&
inst->U.I.Opcode != RC_OPCODE_TXB &&
inst->U.I.Opcode != RC_OPCODE_TXP &&
inst->U.I.Opcode != RC_OPCODE_KIL)
return 0;
/* ARB_shadow & EXT_shadow_funcs */
if (inst->I.Opcode != RC_OPCODE_KIL &&
c->Program.ShadowSamplers & (1 << inst->I.TexSrcUnit)) {
rc_compare_func comparefunc = compiler->state.unit[inst->I.TexSrcUnit].texture_compare_func;
if (inst->U.I.Opcode != RC_OPCODE_KIL &&
c->Program.ShadowSamplers & (1 << inst->U.I.TexSrcUnit)) {
rc_compare_func comparefunc = compiler->state.unit[inst->U.I.TexSrcUnit].texture_compare_func;
if (comparefunc == RC_COMPARE_FUNC_NEVER || comparefunc == RC_COMPARE_FUNC_ALWAYS) {
inst->I.Opcode = RC_OPCODE_MOV;
inst->U.I.Opcode = RC_OPCODE_MOV;
if (comparefunc == RC_COMPARE_FUNC_ALWAYS) {
inst->I.SrcReg[0].File = RC_FILE_NONE;
inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_1111;
inst->U.I.SrcReg[0].File = RC_FILE_NONE;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_1111;
} else {
inst->I.SrcReg[0] = shadow_ambient(c, inst->I.TexSrcUnit);
inst->U.I.SrcReg[0] = shadow_ambient(c, inst->U.I.TexSrcUnit);
}
return 1;
} else {
rc_compare_func comparefunc = compiler->state.unit[inst->I.TexSrcUnit].texture_compare_func;
unsigned int depthmode = compiler->state.unit[inst->I.TexSrcUnit].depth_texture_mode;
rc_compare_func comparefunc = compiler->state.unit[inst->U.I.TexSrcUnit].texture_compare_func;
unsigned int depthmode = compiler->state.unit[inst->U.I.TexSrcUnit].depth_texture_mode;
struct rc_instruction * inst_rcp = rc_insert_new_instruction(c, inst);
struct rc_instruction * inst_mad = rc_insert_new_instruction(c, inst_rcp);
struct rc_instruction * inst_cmp = rc_insert_new_instruction(c, inst_mad);
int pass, fail;
inst_rcp->I.Opcode = RC_OPCODE_RCP;
inst_rcp->I.DstReg.File = RC_FILE_TEMPORARY;
inst_rcp->I.DstReg.Index = rc_find_free_temporary(c);
inst_rcp->I.DstReg.WriteMask = RC_MASK_W;
inst_rcp->I.SrcReg[0] = inst->I.SrcReg[0];
inst_rcp->I.SrcReg[0].Swizzle = RC_SWIZZLE_WWWW;
inst_rcp->U.I.Opcode = RC_OPCODE_RCP;
inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_rcp->U.I.DstReg.Index = rc_find_free_temporary(c);
inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
inst_rcp->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_WWWW;
inst_cmp->I.DstReg = inst->I.DstReg;
inst->I.DstReg.File = RC_FILE_TEMPORARY;
inst->I.DstReg.Index = rc_find_free_temporary(c);
inst->I.DstReg.WriteMask = RC_MASK_XYZW;
inst_cmp->U.I.DstReg = inst->U.I.DstReg;
inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst->U.I.DstReg.Index = rc_find_free_temporary(c);
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
inst_mad->I.Opcode = RC_OPCODE_MAD;
inst_mad->I.DstReg.File = RC_FILE_TEMPORARY;
inst_mad->I.DstReg.Index = rc_find_free_temporary(c);
inst_mad->I.SrcReg[0] = inst->I.SrcReg[0];
inst_mad->I.SrcReg[0].Swizzle = RC_SWIZZLE_ZZZZ;
inst_mad->I.SrcReg[1].File = RC_FILE_TEMPORARY;
inst_mad->I.SrcReg[1].Index = inst_rcp->I.DstReg.Index;
inst_mad->I.SrcReg[1].Swizzle = RC_SWIZZLE_WWWW;
inst_mad->I.SrcReg[2].File = RC_FILE_TEMPORARY;
inst_mad->I.SrcReg[2].Index = inst->I.DstReg.Index;
inst_mad->U.I.Opcode = RC_OPCODE_MAD;
inst_mad->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_mad->U.I.DstReg.Index = rc_find_free_temporary(c);
inst_mad->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
inst_mad->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_ZZZZ;
inst_mad->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
inst_mad->U.I.SrcReg[1].Index = inst_rcp->U.I.DstReg.Index;
inst_mad->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_WWWW;
inst_mad->U.I.SrcReg[2].File = RC_FILE_TEMPORARY;
inst_mad->U.I.SrcReg[2].Index = inst->U.I.DstReg.Index;
if (depthmode == 0) /* GL_LUMINANCE */
inst_mad->I.SrcReg[2].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_Z);
inst_mad->U.I.SrcReg[2].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_Z);
else if (depthmode == 2) /* GL_ALPHA */
inst_mad->I.SrcReg[2].Swizzle = RC_SWIZZLE_WWWW;
inst_mad->U.I.SrcReg[2].Swizzle = RC_SWIZZLE_WWWW;
/* Recall that SrcReg[0] is tex, SrcReg[2] is r and:
* r < tex <=> -tex+r < 0
* r >= tex <=> not (-tex+r < 0 */
if (comparefunc == RC_COMPARE_FUNC_LESS || comparefunc == RC_COMPARE_FUNC_GEQUAL)
inst_mad->I.SrcReg[2].Negate = inst_mad->I.SrcReg[2].Negate ^ RC_MASK_XYZW;
inst_mad->U.I.SrcReg[2].Negate = inst_mad->U.I.SrcReg[2].Negate ^ RC_MASK_XYZW;
else
inst_mad->I.SrcReg[0].Negate = inst_mad->I.SrcReg[0].Negate ^ RC_MASK_XYZW;
inst_mad->U.I.SrcReg[0].Negate = inst_mad->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW;
inst_cmp->I.Opcode = RC_OPCODE_CMP;
inst_cmp->U.I.Opcode = RC_OPCODE_CMP;
/* DstReg has been filled out above */
inst_cmp->I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_cmp->I.SrcReg[0].Index = inst_mad->I.DstReg.Index;
inst_cmp->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_cmp->U.I.SrcReg[0].Index = inst_mad->U.I.DstReg.Index;
if (comparefunc == RC_COMPARE_FUNC_LESS || comparefunc == RC_COMPARE_FUNC_GREATER) {
pass = 1;
@ -133,9 +133,9 @@ int r300_transform_TEX(
fail = 1;
}
inst_cmp->I.SrcReg[pass].File = RC_FILE_NONE;
inst_cmp->I.SrcReg[pass].Swizzle = RC_SWIZZLE_1111;
inst_cmp->I.SrcReg[fail] = shadow_ambient(c, inst->I.TexSrcUnit);
inst_cmp->U.I.SrcReg[pass].File = RC_FILE_NONE;
inst_cmp->U.I.SrcReg[pass].Swizzle = RC_SWIZZLE_1111;
inst_cmp->U.I.SrcReg[fail] = shadow_ambient(c, inst->U.I.TexSrcUnit);
}
}
@ -143,49 +143,49 @@ int r300_transform_TEX(
* instead of [0..Width]x[0..Height].
* Add a scaling instruction.
*/
if (inst->I.Opcode != RC_OPCODE_KIL && inst->I.TexSrcTarget == RC_TEXTURE_RECT) {
if (inst->U.I.Opcode != RC_OPCODE_KIL && inst->U.I.TexSrcTarget == RC_TEXTURE_RECT) {
struct rc_instruction * inst_mul = rc_insert_new_instruction(c, inst->Prev);
inst_mul->I.Opcode = RC_OPCODE_MUL;
inst_mul->I.DstReg.File = RC_FILE_TEMPORARY;
inst_mul->I.DstReg.Index = rc_find_free_temporary(c);
inst_mul->I.SrcReg[0] = inst->I.SrcReg[0];
inst_mul->I.SrcReg[1].File = RC_FILE_CONSTANT;
inst_mul->I.SrcReg[1].Index = rc_constants_add_state(&c->Program.Constants, RC_STATE_R300_TEXRECT_FACTOR, inst->I.TexSrcUnit);
inst_mul->U.I.Opcode = RC_OPCODE_MUL;
inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_mul->U.I.DstReg.Index = rc_find_free_temporary(c);
inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
inst_mul->U.I.SrcReg[1].File = RC_FILE_CONSTANT;
inst_mul->U.I.SrcReg[1].Index = rc_constants_add_state(&c->Program.Constants, RC_STATE_R300_TEXRECT_FACTOR, inst->U.I.TexSrcUnit);
reset_srcreg(&inst->I.SrcReg[0]);
inst->I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst->I.SrcReg[0].Index = inst_mul->I.DstReg.Index;
reset_srcreg(&inst->U.I.SrcReg[0]);
inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst->U.I.SrcReg[0].Index = inst_mul->U.I.DstReg.Index;
}
/* Cannot write texture to output registers or with masks */
if (inst->I.Opcode != RC_OPCODE_KIL &&
(inst->I.DstReg.File != RC_FILE_TEMPORARY || inst->I.DstReg.WriteMask != RC_MASK_XYZW)) {
if (inst->U.I.Opcode != RC_OPCODE_KIL &&
(inst->U.I.DstReg.File != RC_FILE_TEMPORARY || inst->U.I.DstReg.WriteMask != RC_MASK_XYZW)) {
struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst);
inst_mov->I.Opcode = RC_OPCODE_MOV;
inst_mov->I.DstReg = inst->I.DstReg;
inst_mov->I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_mov->I.SrcReg[0].Index = rc_find_free_temporary(c);
inst_mov->U.I.Opcode = RC_OPCODE_MOV;
inst_mov->U.I.DstReg = inst->U.I.DstReg;
inst_mov->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_mov->U.I.SrcReg[0].Index = rc_find_free_temporary(c);
inst->I.DstReg.File = RC_FILE_TEMPORARY;
inst->I.DstReg.Index = inst_mov->I.SrcReg[0].Index;
inst->I.DstReg.WriteMask = RC_MASK_XYZW;
inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst->U.I.DstReg.Index = inst_mov->U.I.SrcReg[0].Index;
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
}
/* Cannot read texture coordinate from constants file */
if (inst->I.SrcReg[0].File != RC_FILE_TEMPORARY && inst->I.SrcReg[0].File != RC_FILE_INPUT) {
if (inst->U.I.SrcReg[0].File != RC_FILE_TEMPORARY && inst->U.I.SrcReg[0].File != RC_FILE_INPUT) {
struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst->Prev);
inst_mov->I.Opcode = RC_OPCODE_MOV;
inst_mov->I.DstReg.File = RC_FILE_TEMPORARY;
inst_mov->I.DstReg.Index = rc_find_free_temporary(c);
inst_mov->I.SrcReg[0] = inst->I.SrcReg[0];
inst_mov->U.I.Opcode = RC_OPCODE_MOV;
inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_mov->U.I.DstReg.Index = rc_find_free_temporary(c);
inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
reset_srcreg(&inst->I.SrcReg[0]);
inst->I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst->I.SrcReg[0].Index = inst_mov->I.DstReg.Index;
reset_srcreg(&inst->U.I.SrcReg[0]);
inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index;
}
return 1;

2
src/mesa/drivers/dri/r300/compiler/r3xx_fragprog.c
View File

@ -44,7 +44,7 @@ static void rewrite_depth_out(struct r300_fragment_program_compiler * c)
struct rc_instruction *rci;
for (rci = c->Base.Program.Instructions.Next; rci != &c->Base.Program.Instructions; rci = rci->Next) {
struct rc_sub_instruction * inst = &rci->I;
struct rc_sub_instruction * inst = &rci->U.I;
if (inst->DstReg.File != RC_FILE_OUTPUT || inst->DstReg.Index != c->OutputDepth)
continue;

86
src/mesa/drivers/dri/r300/compiler/r3xx_vertprog.c
View File

@ -341,7 +341,7 @@ static void translate_vertex_program(struct r300_vertex_program_compiler * compi
compiler->SetHwInputOutput(compiler);
for(rci = compiler->Base.Program.Instructions.Next; rci != &compiler->Base.Program.Instructions; rci = rci->Next) {
struct rc_sub_instruction *vpi = &rci->I;
struct rc_sub_instruction *vpi = &rci->U.I;
unsigned int *inst = compiler->code->body.d + compiler->code->length;
/* Skip instructions writing to non-existing destination */
@ -405,19 +405,19 @@ static void allocate_temporary_registers(struct r300_vertex_program_compiler * c
/* Pass 1: Count original temporaries and allocate structures */
for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) {
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
for (i = 0; i < opcode->NumSrcRegs; ++i) {
if (inst->I.SrcReg[i].File == RC_FILE_TEMPORARY) {
if (inst->I.SrcReg[i].Index >= num_orig_temps)
num_orig_temps = inst->I.SrcReg[i].Index + 1;
if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) {
if (inst->U.I.SrcReg[i].Index >= num_orig_temps)
num_orig_temps = inst->U.I.SrcReg[i].Index + 1;
}
}
if (opcode->HasDstReg) {
if (inst->I.DstReg.File == RC_FILE_TEMPORARY) {
if (inst->I.DstReg.Index >= num_orig_temps)
num_orig_temps = inst->I.DstReg.Index + 1;
if (inst->U.I.DstReg.File == RC_FILE_TEMPORARY) {
if (inst->U.I.DstReg.Index >= num_orig_temps)
num_orig_temps = inst->U.I.DstReg.Index + 1;
}
}
}
@ -428,22 +428,22 @@ static void allocate_temporary_registers(struct r300_vertex_program_compiler * c
/* Pass 2: Determine original temporary lifetimes */
for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) {
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
for (i = 0; i < opcode->NumSrcRegs; ++i) {
if (inst->I.SrcReg[i].File == RC_FILE_TEMPORARY)
ta[inst->I.SrcReg[i].Index].LastRead = inst;
if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY)
ta[inst->U.I.SrcReg[i].Index].LastRead = inst;
}
}
/* Pass 3: Register allocation */
for(inst = compiler->Base.Program.Instructions.Next; inst != &compiler->Base.Program.Instructions; inst = inst->Next) {
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
for (i = 0; i < opcode->NumSrcRegs; ++i) {
if (inst->I.SrcReg[i].File == RC_FILE_TEMPORARY) {
unsigned int orig = inst->I.SrcReg[i].Index;
inst->I.SrcReg[i].Index = ta[orig].HwTemp;
if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY) {
unsigned int orig = inst->U.I.SrcReg[i].Index;
inst->U.I.SrcReg[i].Index = ta[orig].HwTemp;
if (ta[orig].Allocated && inst == ta[orig].LastRead)
hwtemps[ta[orig].HwTemp] = 0;
@ -451,8 +451,8 @@ static void allocate_temporary_registers(struct r300_vertex_program_compiler * c
}
if (opcode->HasDstReg) {
if (inst->I.DstReg.File == RC_FILE_TEMPORARY) {
unsigned int orig = inst->I.DstReg.Index;
if (inst->U.I.DstReg.File == RC_FILE_TEMPORARY) {
unsigned int orig = inst->U.I.DstReg.Index;
if (!ta[orig].Allocated) {
for(j = 0; j < VSF_MAX_FRAGMENT_TEMPS; ++j) {
@ -471,7 +471,7 @@ static void allocate_temporary_registers(struct r300_vertex_program_compiler * c
}
}
inst->I.DstReg.Index = ta[orig].HwTemp;
inst->U.I.DstReg.Index = ta[orig].HwTemp;
}
}
}
@ -487,36 +487,36 @@ static int transform_source_conflicts(
struct rc_instruction* inst,
void* unused)
{
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
if (opcode->NumSrcRegs == 3) {
if (t_src_conflict(inst->I.SrcReg[1], inst->I.SrcReg[2])
|| t_src_conflict(inst->I.SrcReg[0], inst->I.SrcReg[2])) {
if (t_src_conflict(inst->U.I.SrcReg[1], inst->U.I.SrcReg[2])
|| t_src_conflict(inst->U.I.SrcReg[0], inst->U.I.SrcReg[2])) {
int tmpreg = rc_find_free_temporary(c);
struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst->Prev);
inst_mov->I.Opcode = RC_OPCODE_MOV;
inst_mov->I.DstReg.File = RC_FILE_TEMPORARY;
inst_mov->I.DstReg.Index = tmpreg;
inst_mov->I.SrcReg[0] = inst->I.SrcReg[2];
inst_mov->U.I.Opcode = RC_OPCODE_MOV;
inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_mov->U.I.DstReg.Index = tmpreg;
inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[2];
reset_srcreg(&inst->I.SrcReg[2]);
inst->I.SrcReg[2].File = RC_FILE_TEMPORARY;
inst->I.SrcReg[2].Index = tmpreg;
reset_srcreg(&inst->U.I.SrcReg[2]);
inst->U.I.SrcReg[2].File = RC_FILE_TEMPORARY;
inst->U.I.SrcReg[2].Index = tmpreg;
}
}
if (opcode->NumSrcRegs >= 2) {
if (t_src_conflict(inst->I.SrcReg[1], inst->I.SrcReg[0])) {
if (t_src_conflict(inst->U.I.SrcReg[1], inst->U.I.SrcReg[0])) {
int tmpreg = rc_find_free_temporary(c);
struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst->Prev);
inst_mov->I.Opcode = RC_OPCODE_MOV;
inst_mov->I.DstReg.File = RC_FILE_TEMPORARY;
inst_mov->I.DstReg.Index = tmpreg;
inst_mov->I.SrcReg[0] = inst->I.SrcReg[1];
inst_mov->U.I.Opcode = RC_OPCODE_MOV;
inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_mov->U.I.DstReg.Index = tmpreg;
inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[1];
reset_srcreg(&inst->I.SrcReg[1]);
inst->I.SrcReg[1].File = RC_FILE_TEMPORARY;
inst->I.SrcReg[1].Index = tmpreg;
reset_srcreg(&inst->U.I.SrcReg[1]);
inst->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
inst->U.I.SrcReg[1].Index = tmpreg;
}
}
@ -531,15 +531,15 @@ static void addArtificialOutputs(struct r300_vertex_program_compiler * compiler)
if ((compiler->RequiredOutputs & (1 << i)) &&
!(compiler->Base.Program.OutputsWritten & (1 << i))) {
struct rc_instruction * inst = rc_insert_new_instruction(&compiler->Base, compiler->Base.Program.Instructions.Prev);
inst->I.Opcode = RC_OPCODE_MOV;
inst->U.I.Opcode = RC_OPCODE_MOV;
inst->I.DstReg.File = RC_FILE_OUTPUT;
inst->I.DstReg.Index = i;
inst->I.DstReg.WriteMask = RC_MASK_XYZW;
inst->U.I.DstReg.File = RC_FILE_OUTPUT;
inst->U.I.DstReg.Index = i;
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
inst->I.SrcReg[0].File = RC_FILE_CONSTANT;
inst->I.SrcReg[0].Index = 0;
inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
inst->U.I.SrcReg[0].File = RC_FILE_CONSTANT;
inst->U.I.SrcReg[0].Index = 0;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
compiler->Base.Program.OutputsWritten |= 1 << i;
}

140
src/mesa/drivers/dri/r300/compiler/r500_fragprog.c
View File

@ -54,75 +54,75 @@ int r500_transform_TEX(
struct r300_fragment_program_compiler *compiler =
(struct r300_fragment_program_compiler*)data;
if (inst->I.Opcode != RC_OPCODE_TEX &&
inst->I.Opcode != RC_OPCODE_TXB &&
inst->I.Opcode != RC_OPCODE_TXP &&
inst->I.Opcode != RC_OPCODE_KIL)
if (inst->U.I.Opcode != RC_OPCODE_TEX &&
inst->U.I.Opcode != RC_OPCODE_TXB &&
inst->U.I.Opcode != RC_OPCODE_TXP &&
inst->U.I.Opcode != RC_OPCODE_KIL)
return 0;
/* ARB_shadow & EXT_shadow_funcs */
if (inst->I.Opcode != RC_OPCODE_KIL &&
c->Program.ShadowSamplers & (1 << inst->I.TexSrcUnit)) {
rc_compare_func comparefunc = compiler->state.unit[inst->I.TexSrcUnit].texture_compare_func;
if (inst->U.I.Opcode != RC_OPCODE_KIL &&
c->Program.ShadowSamplers & (1 << inst->U.I.TexSrcUnit)) {
rc_compare_func comparefunc = compiler->state.unit[inst->U.I.TexSrcUnit].texture_compare_func;
if (comparefunc == RC_COMPARE_FUNC_NEVER || comparefunc == RC_COMPARE_FUNC_ALWAYS) {
inst->I.Opcode = RC_OPCODE_MOV;
inst->U.I.Opcode = RC_OPCODE_MOV;
if (comparefunc == RC_COMPARE_FUNC_ALWAYS) {
inst->I.SrcReg[0].File = RC_FILE_NONE;
inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_1111;
inst->U.I.SrcReg[0].File = RC_FILE_NONE;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_1111;
} else {
inst->I.SrcReg[0] = shadow_ambient(c, inst->I.TexSrcUnit);
inst->U.I.SrcReg[0] = shadow_ambient(c, inst->U.I.TexSrcUnit);
}
return 1;
} else {
rc_compare_func comparefunc = compiler->state.unit[inst->I.TexSrcUnit].texture_compare_func;
unsigned int depthmode = compiler->state.unit[inst->I.TexSrcUnit].depth_texture_mode;
rc_compare_func comparefunc = compiler->state.unit[inst->U.I.TexSrcUnit].texture_compare_func;
unsigned int depthmode = compiler->state.unit[inst->U.I.TexSrcUnit].depth_texture_mode;
struct rc_instruction * inst_rcp = rc_insert_new_instruction(c, inst);
struct rc_instruction * inst_mad = rc_insert_new_instruction(c, inst_rcp);
struct rc_instruction * inst_cmp = rc_insert_new_instruction(c, inst_mad);
int pass, fail;
inst_rcp->I.Opcode = RC_OPCODE_RCP;
inst_rcp->I.DstReg.File = RC_FILE_TEMPORARY;
inst_rcp->I.DstReg.Index = rc_find_free_temporary(c);
inst_rcp->I.DstReg.WriteMask = RC_MASK_W;
inst_rcp->I.SrcReg[0] = inst->I.SrcReg[0];
inst_rcp->I.SrcReg[0].Swizzle = RC_SWIZZLE_WWWW;
inst_rcp->U.I.Opcode = RC_OPCODE_RCP;
inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_rcp->U.I.DstReg.Index = rc_find_free_temporary(c);
inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
inst_rcp->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_WWWW;
inst_cmp->I.DstReg = inst->I.DstReg;
inst->I.DstReg.File = RC_FILE_TEMPORARY;
inst->I.DstReg.Index = rc_find_free_temporary(c);
inst->I.DstReg.WriteMask = RC_MASK_XYZW;
inst_cmp->U.I.DstReg = inst->U.I.DstReg;
inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst->U.I.DstReg.Index = rc_find_free_temporary(c);
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
inst_mad->I.Opcode = RC_OPCODE_MAD;
inst_mad->I.DstReg.File = RC_FILE_TEMPORARY;
inst_mad->I.DstReg.Index = rc_find_free_temporary(c);
inst_mad->I.SrcReg[0] = inst->I.SrcReg[0];
inst_mad->I.SrcReg[0].Swizzle = RC_SWIZZLE_ZZZZ;
inst_mad->I.SrcReg[1].File = RC_FILE_TEMPORARY;
inst_mad->I.SrcReg[1].Index = inst_rcp->I.DstReg.Index;
inst_mad->I.SrcReg[1].Swizzle = RC_SWIZZLE_WWWW;
inst_mad->I.SrcReg[2].File = RC_FILE_TEMPORARY;
inst_mad->I.SrcReg[2].Index = inst->I.DstReg.Index;
inst_mad->U.I.Opcode = RC_OPCODE_MAD;
inst_mad->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_mad->U.I.DstReg.Index = rc_find_free_temporary(c);
inst_mad->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
inst_mad->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_ZZZZ;
inst_mad->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
inst_mad->U.I.SrcReg[1].Index = inst_rcp->U.I.DstReg.Index;
inst_mad->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_WWWW;
inst_mad->U.I.SrcReg[2].File = RC_FILE_TEMPORARY;
inst_mad->U.I.SrcReg[2].Index = inst->U.I.DstReg.Index;
if (depthmode == 0) /* GL_LUMINANCE */
inst_mad->I.SrcReg[2].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_Z);
inst_mad->U.I.SrcReg[2].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_Z);
else if (depthmode == 2) /* GL_ALPHA */
inst_mad->I.SrcReg[2].Swizzle = RC_SWIZZLE_WWWW;
inst_mad->U.I.SrcReg[2].Swizzle = RC_SWIZZLE_WWWW;
/* Recall that SrcReg[0] is tex, SrcReg[2] is r and:
* r < tex <=> -tex+r < 0
* r >= tex <=> not (-tex+r < 0 */
if (comparefunc == RC_COMPARE_FUNC_LESS || comparefunc == RC_COMPARE_FUNC_GEQUAL)
inst_mad->I.SrcReg[2].Negate = inst_mad->I.SrcReg[2].Negate ^ RC_MASK_XYZW;
inst_mad->U.I.SrcReg[2].Negate = inst_mad->U.I.SrcReg[2].Negate ^ RC_MASK_XYZW;
else
inst_mad->I.SrcReg[0].Negate = inst_mad->I.SrcReg[0].Negate ^ RC_MASK_XYZW;
inst_mad->U.I.SrcReg[0].Negate = inst_mad->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW;
inst_cmp->I.Opcode = RC_OPCODE_CMP;
inst_cmp->U.I.Opcode = RC_OPCODE_CMP;
/* DstReg has been filled out above */
inst_cmp->I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_cmp->I.SrcReg[0].Index = inst_mad->I.DstReg.Index;
inst_cmp->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_cmp->U.I.SrcReg[0].Index = inst_mad->U.I.DstReg.Index;
if (comparefunc == RC_COMPARE_FUNC_LESS || comparefunc == RC_COMPARE_FUNC_GREATER) {
pass = 1;
@ -132,38 +132,38 @@ int r500_transform_TEX(
fail = 1;
}
inst_cmp->I.SrcReg[pass].File = RC_FILE_NONE;
inst_cmp->I.SrcReg[pass].Swizzle = RC_SWIZZLE_1111;
inst_cmp->I.SrcReg[fail] = shadow_ambient(c, inst->I.TexSrcUnit);
inst_cmp->U.I.SrcReg[pass].File = RC_FILE_NONE;
inst_cmp->U.I.SrcReg[pass].Swizzle = RC_SWIZZLE_1111;
inst_cmp->U.I.SrcReg[fail] = shadow_ambient(c, inst->U.I.TexSrcUnit);
}
}
/* Cannot write texture to output registers */
if (inst->I.Opcode != RC_OPCODE_KIL && inst->I.DstReg.File != RC_FILE_TEMPORARY) {
if (inst->U.I.Opcode != RC_OPCODE_KIL && inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst);
inst_mov->I.Opcode = RC_OPCODE_MOV;
inst_mov->I.DstReg = inst->I.DstReg;
inst_mov->I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_mov->I.SrcReg[0].Index = rc_find_free_temporary(c);
inst_mov->U.I.Opcode = RC_OPCODE_MOV;
inst_mov->U.I.DstReg = inst->U.I.DstReg;
inst_mov->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_mov->U.I.SrcReg[0].Index = rc_find_free_temporary(c);
inst->I.DstReg.File = RC_FILE_TEMPORARY;
inst->I.DstReg.Index = inst_mov->I.SrcReg[0].Index;
inst->I.DstReg.WriteMask = RC_MASK_XYZW;
inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst->U.I.DstReg.Index = inst_mov->U.I.SrcReg[0].Index;
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
}
/* Cannot read texture coordinate from constants file */
if (inst->I.SrcReg[0].File != RC_FILE_TEMPORARY && inst->I.SrcReg[0].File != RC_FILE_INPUT) {
if (inst->U.I.SrcReg[0].File != RC_FILE_TEMPORARY && inst->U.I.SrcReg[0].File != RC_FILE_INPUT) {
struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst->Prev);
inst_mov->I.Opcode = RC_OPCODE_MOV;
inst_mov->I.DstReg.File = RC_FILE_TEMPORARY;
inst_mov->I.DstReg.Index = rc_find_free_temporary(c);
inst_mov->I.SrcReg[0] = inst->I.SrcReg[0];
inst_mov->U.I.Opcode = RC_OPCODE_MOV;
inst_mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_mov->U.I.DstReg.Index = rc_find_free_temporary(c);
inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
reset_srcreg(&inst->I.SrcReg[0]);
inst->I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst->I.SrcReg[0].Index = inst_mov->I.DstReg.Index;
reset_srcreg(&inst->U.I.SrcReg[0]);
inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index;
}
return 1;
@ -177,22 +177,22 @@ int r500_transform_IF(
struct rc_instruction * inst,
void* data)
{
if (inst->I.Opcode != RC_OPCODE_IF)
if (inst->U.I.Opcode != RC_OPCODE_IF)
return 0;
struct rc_instruction * inst_mov = rc_insert_new_instruction(c, inst->Prev);
inst_mov->I.Opcode = RC_OPCODE_MOV;
inst_mov->I.DstReg.WriteMask = 0;
inst_mov->I.WriteALUResult = RC_ALURESULT_W;
inst_mov->I.ALUResultCompare = RC_COMPARE_FUNC_NOTEQUAL;
inst_mov->I.SrcReg[0] = inst->I.SrcReg[0];
inst_mov->I.SrcReg[0].Swizzle = combine_swizzles4(inst_mov->I.SrcReg[0].Swizzle,
inst_mov->U.I.Opcode = RC_OPCODE_MOV;
inst_mov->U.I.DstReg.WriteMask = 0;
inst_mov->U.I.WriteALUResult = RC_ALURESULT_W;
inst_mov->U.I.ALUResultCompare = RC_COMPARE_FUNC_NOTEQUAL;
inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(inst_mov->U.I.SrcReg[0].Swizzle,
RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED, RC_SWIZZLE_UNUSED, RC_SWIZZLE_X);
inst->I.SrcReg[0].File = RC_FILE_SPECIAL;
inst->I.SrcReg[0].Index = RC_SPECIAL_ALU_RESULT;
inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
inst->I.SrcReg[0].Negate = 0;
inst->U.I.SrcReg[0].File = RC_FILE_SPECIAL;
inst->U.I.SrcReg[0].Index = RC_SPECIAL_ALU_RESULT;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
inst->U.I.SrcReg[0].Negate = 0;
return 1;
}

136
src/mesa/drivers/dri/r300/compiler/radeon_compiler.c
View File

@ -36,7 +36,7 @@ void rc_init(struct radeon_compiler * c)
memory_pool_init(&c->Pool);
c->Program.Instructions.Prev = &c->Program.Instructions;
c->Program.Instructions.Next = &c->Program.Instructions;
c->Program.Instructions.I.Opcode = RC_OPCODE_ILLEGAL_OPCODE;
c->Program.Instructions.U.I.Opcode = RC_OPCODE_ILLEGAL_OPCODE;
}
void rc_destroy(struct radeon_compiler * c)
@ -113,17 +113,17 @@ void rc_calculate_inputs_outputs(struct radeon_compiler * c)
for(inst = c->Program.Instructions.Next; inst != &c->Program.Instructions; inst = inst->Next)
{
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
int i;
for (i = 0; i < opcode->NumSrcRegs; ++i) {
if (inst->I.SrcReg[i].File == RC_FILE_INPUT)
c->Program.InputsRead |= 1 << inst->I.SrcReg[i].Index;
if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT)
c->Program.InputsRead |= 1 << inst->U.I.SrcReg[i].Index;
}
if (opcode->HasDstReg) {
if (inst->I.DstReg.File == RC_FILE_OUTPUT)
c->Program.OutputsWritten |= 1 << inst->I.DstReg.Index;
if (inst->U.I.DstReg.File == RC_FILE_OUTPUT)
c->Program.OutputsWritten |= 1 << inst->U.I.DstReg.Index;
}
}
}
@ -139,17 +139,17 @@ void rc_move_input(struct radeon_compiler * c, unsigned input, struct rc_src_reg
c->Program.InputsRead &= ~(1 << input);
for(inst = c->Program.Instructions.Next; inst != &c->Program.Instructions; inst = inst->Next) {
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
unsigned i;
for(i = 0; i < opcode->NumSrcRegs; ++i) {
if (inst->I.SrcReg[i].File == RC_FILE_INPUT && inst->I.SrcReg[i].Index == input) {
inst->I.SrcReg[i].File = new_input.File;
inst->I.SrcReg[i].Index = new_input.Index;
inst->I.SrcReg[i].Swizzle = combine_swizzles(new_input.Swizzle, inst->I.SrcReg[i].Swizzle);
if (!inst->I.SrcReg[i].Abs) {
inst->I.SrcReg[i].Negate ^= new_input.Negate;
inst->I.SrcReg[i].Abs = new_input.Abs;
if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT && inst->U.I.SrcReg[i].Index == input) {
inst->U.I.SrcReg[i].File = new_input.File;
inst->U.I.SrcReg[i].Index = new_input.Index;
inst->U.I.SrcReg[i].Swizzle = combine_swizzles(new_input.Swizzle, inst->U.I.SrcReg[i].Swizzle);
if (!inst->U.I.SrcReg[i].Abs) {
inst->U.I.SrcReg[i].Negate ^= new_input.Negate;
inst->U.I.SrcReg[i].Abs = new_input.Abs;
}
c->Program.InputsRead |= 1 << new_input.Index;
@ -171,12 +171,12 @@ void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_ou
c->Program.OutputsWritten &= ~(1 << output);
for(inst = c->Program.Instructions.Next; inst != &c->Program.Instructions; inst = inst->Next) {
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
if (opcode->HasDstReg) {
if (inst->I.DstReg.File == RC_FILE_OUTPUT && inst->I.DstReg.Index == output) {
inst->I.DstReg.Index = new_output;
inst->I.DstReg.WriteMask &= writemask;
if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) {
inst->U.I.DstReg.Index = new_output;
inst->U.I.DstReg.WriteMask &= writemask;
c->Program.OutputsWritten |= 1 << new_output;
}
@ -194,33 +194,33 @@ void rc_copy_output(struct radeon_compiler * c, unsigned output, unsigned dup_ou
struct rc_instruction * inst;
for(inst = c->Program.Instructions.Next; inst != &c->Program.Instructions; inst = inst->Next) {
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
if (opcode->HasDstReg) {
if (inst->I.DstReg.File == RC_FILE_OUTPUT && inst->I.DstReg.Index == output) {
inst->I.DstReg.File = RC_FILE_TEMPORARY;
inst->I.DstReg.Index = tempreg;
if (inst->U.I.DstReg.File == RC_FILE_OUTPUT && inst->U.I.DstReg.Index == output) {
inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst->U.I.DstReg.Index = tempreg;
}
}
}
inst = rc_insert_new_instruction(c, c->Program.Instructions.Prev);
inst->I.Opcode = RC_OPCODE_MOV;
inst->I.DstReg.File = RC_FILE_OUTPUT;
inst->I.DstReg.Index = output;
inst->U.I.Opcode = RC_OPCODE_MOV;
inst->U.I.DstReg.File = RC_FILE_OUTPUT;
inst->U.I.DstReg.Index = output;
inst->I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst->I.SrcReg[0].Index = tempreg;
inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst->U.I.SrcReg[0].Index = tempreg;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
inst = rc_insert_new_instruction(c, c->Program.Instructions.Prev);
inst->I.Opcode = RC_OPCODE_MOV;
inst->I.DstReg.File = RC_FILE_OUTPUT;
inst->I.DstReg.Index = dup_output;
inst->U.I.Opcode = RC_OPCODE_MOV;
inst->U.I.DstReg.File = RC_FILE_OUTPUT;
inst->U.I.DstReg.Index = dup_output;
inst->I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst->I.SrcReg[0].Index = tempreg;
inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst->U.I.SrcReg[0].Index = tempreg;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
c->Program.OutputsWritten |= 1 << dup_output;
}
@ -238,60 +238,60 @@ void rc_transform_fragment_wpos(struct radeon_compiler * c, unsigned wpos, unsig
/* perspective divide */
struct rc_instruction * inst_rcp = rc_insert_new_instruction(c, &c->Program.Instructions);
inst_rcp->I.Opcode = RC_OPCODE_RCP;
inst_rcp->U.I.Opcode = RC_OPCODE_RCP;
inst_rcp->I.DstReg.File = RC_FILE_TEMPORARY;
inst_rcp->I.DstReg.Index = tempregi;
inst_rcp->I.DstReg.WriteMask = RC_MASK_W;
inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_rcp->U.I.DstReg.Index = tempregi;
inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
inst_rcp->I.SrcReg[0].File = RC_FILE_INPUT;
inst_rcp->I.SrcReg[0].Index = new_input;
inst_rcp->I.SrcReg[0].Swizzle = RC_SWIZZLE_WWWW;
inst_rcp->U.I.SrcReg[0].File = RC_FILE_INPUT;
inst_rcp->U.I.SrcReg[0].Index = new_input;
inst_rcp->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_WWWW;
struct rc_instruction * inst_mul = rc_insert_new_instruction(c, inst_rcp);
inst_mul->I.Opcode = RC_OPCODE_MUL;
inst_mul->U.I.Opcode = RC_OPCODE_MUL;
inst_mul->I.DstReg.File = RC_FILE_TEMPORARY;
inst_mul->I.DstReg.Index = tempregi;
inst_mul->I.DstReg.WriteMask = RC_MASK_XYZ;
inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_mul->U.I.DstReg.Index = tempregi;
inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ;
inst_mul->I.SrcReg[0].File = RC_FILE_INPUT;
inst_mul->I.SrcReg[0].Index = new_input;
inst_mul->U.I.SrcReg[0].File = RC_FILE_INPUT;
inst_mul->U.I.SrcReg[0].Index = new_input;
inst_mul->I.SrcReg[1].File = RC_FILE_TEMPORARY;
inst_mul->I.SrcReg[1].Index = tempregi;
inst_mul->I.SrcReg[1].Swizzle = RC_SWIZZLE_WWWW;
inst_mul->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
inst_mul->U.I.SrcReg[1].Index = tempregi;
inst_mul->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_WWWW;
/* viewport transformation */
struct rc_instruction * inst_mad = rc_insert_new_instruction(c, inst_mul);
inst_mad->I.Opcode = RC_OPCODE_MAD;
inst_mad->U.I.Opcode = RC_OPCODE_MAD;
inst_mad->I.DstReg.File = RC_FILE_TEMPORARY;
inst_mad->I.DstReg.Index = tempregi;
inst_mad->I.DstReg.WriteMask = RC_MASK_XYZ;
inst_mad->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst_mad->U.I.DstReg.Index = tempregi;
inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ;
inst_mad->I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_mad->I.SrcReg[0].Index = tempregi;
inst_mad->I.SrcReg[0].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ZERO);
inst_mad->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
inst_mad->U.I.SrcReg[0].Index = tempregi;
inst_mad->U.I.SrcReg[0].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ZERO);
inst_mad->I.SrcReg[1].File = RC_FILE_CONSTANT;
inst_mad->I.SrcReg[1].Index = rc_constants_add_state(&c->Program.Constants, RC_STATE_R300_WINDOW_DIMENSION, 0);
inst_mad->I.SrcReg[1].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ZERO);
inst_mad->U.I.SrcReg[1].File = RC_FILE_CONSTANT;
inst_mad->U.I.SrcReg[1].Index = rc_constants_add_state(&c->Program.Constants, RC_STATE_R300_WINDOW_DIMENSION, 0);
inst_mad->U.I.SrcReg[1].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ZERO);
inst_mad->I.SrcReg[2].File = RC_FILE_CONSTANT;
inst_mad->I.SrcReg[2].Index = inst_mad->I.SrcReg[1].Index;
inst_mad->I.SrcReg[2].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ZERO);
inst_mad->U.I.SrcReg[2].File = RC_FILE_CONSTANT;
inst_mad->U.I.SrcReg[2].Index = inst_mad->U.I.SrcReg[1].Index;
inst_mad->U.I.SrcReg[2].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ZERO);
struct rc_instruction * inst;
for (inst = inst_mad->Next; inst != &c->Program.Instructions; inst = inst->Next) {
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
unsigned i;
for(i = 0; i < opcode->NumSrcRegs; i++) {
if (inst->I.SrcReg[i].File == RC_FILE_INPUT &&
inst->I.SrcReg[i].Index == wpos) {
inst->I.SrcReg[i].File = RC_FILE_TEMPORARY;
inst->I.SrcReg[i].Index = tempregi;
if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT &&
inst->U.I.SrcReg[i].Index == wpos) {
inst->U.I.SrcReg[i].File = RC_FILE_TEMPORARY;
inst->U.I.SrcReg[i].Index = tempregi;
}
}
}

32
src/mesa/drivers/dri/r300/compiler/radeon_dataflow_deadcode.c
View File

@ -134,26 +134,26 @@ static void mark_used(struct deadcode_state * s, rc_register_file file, unsigned
static void update_instruction(struct deadcode_state * s, struct rc_instruction * inst)
{
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
struct instruction_state * insts = &s->Instructions[inst->IP];
unsigned int usedmask = 0;
if (opcode->HasDstReg) {
unsigned char * pused = get_used_ptr(s, inst->I.DstReg.File, inst->I.DstReg.Index);
unsigned char * pused = get_used_ptr(s, inst->U.I.DstReg.File, inst->U.I.DstReg.Index);
if (pused) {
usedmask = *pused & inst->I.DstReg.WriteMask;
usedmask = *pused & inst->U.I.DstReg.WriteMask;
*pused &= ~usedmask;
}
}
insts->WriteMask |= usedmask;
if (inst->I.WriteALUResult) {
if (inst->U.I.WriteALUResult) {
unsigned char * pused = get_used_ptr(s, RC_FILE_SPECIAL, RC_SPECIAL_ALU_RESULT);
if (pused && *pused) {
if (inst->I.WriteALUResult == RC_ALURESULT_X)
if (inst->U.I.WriteALUResult == RC_ALURESULT_X)
usedmask |= RC_MASK_X;
else if (inst->I.WriteALUResult == RC_ALURESULT_W)
else if (inst->U.I.WriteALUResult == RC_ALURESULT_W)
usedmask |= RC_MASK_W;
*pused = 0;
@ -171,7 +171,7 @@ static void update_instruction(struct deadcode_state * s, struct rc_instruction
for(unsigned int chan = 0; chan < 4; ++chan) {
if (GET_BIT(newsrcmask, chan))
refmask |= 1 << GET_SWZ(inst->I.SrcReg[src].Swizzle, chan);
refmask |= 1 << GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan);
}
/* get rid of spurious bits from ZERO, ONE, etc. swizzles */
@ -180,9 +180,9 @@ static void update_instruction(struct deadcode_state * s, struct rc_instruction
if (!refmask)
continue;
mark_used(s, inst->I.SrcReg[src].File, inst->I.SrcReg[src].Index, refmask);
mark_used(s, inst->U.I.SrcReg[src].File, inst->U.I.SrcReg[src].Index, refmask);
if (inst->I.SrcReg[src].RelAddr)
if (inst->U.I.SrcReg[src].RelAddr)
mark_used(s, RC_FILE_ADDRESS, 0, RC_MASK_X);
}
}
@ -211,7 +211,7 @@ void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_f
for(struct rc_instruction * inst = c->Program.Instructions.Prev;
inst != &c->Program.Instructions;
inst = inst->Prev) {
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
if (opcode->IsControlFlow) {
if (opcode->Opcode == RC_OPCODE_ENDIF) {
@ -250,20 +250,20 @@ void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_f
for(struct rc_instruction * inst = c->Program.Instructions.Next;
inst != &c->Program.Instructions;
inst = inst->Next, ++ip) {
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);\
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);\
int dead = 1;
if (!opcode->HasDstReg) {
dead = 0;
} else {
inst->I.DstReg.WriteMask = s.Instructions[ip].WriteMask;
inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask;
if (s.Instructions[ip].WriteMask)
dead = 0;
if (s.Instructions[ip].WriteALUResult)
dead = 0;
else
inst->I.WriteALUResult = RC_ALURESULT_NONE;
inst->U.I.WriteALUResult = RC_ALURESULT_NONE;
}
if (dead) {
@ -276,9 +276,9 @@ void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_f
unsigned int srcmasks[3];
unsigned int usemask = s.Instructions[ip].WriteMask;
if (inst->I.WriteALUResult == RC_ALURESULT_X)
if (inst->U.I.WriteALUResult == RC_ALURESULT_X)
usemask |= RC_MASK_X;
else if (inst->I.WriteALUResult == RC_ALURESULT_W)
else if (inst->U.I.WriteALUResult == RC_ALURESULT_W)
usemask |= RC_MASK_W;
rc_compute_sources_for_writemask(opcode, usemask, srcmasks);
@ -286,7 +286,7 @@ void rc_dataflow_deadcode(struct radeon_compiler * c, rc_dataflow_mark_outputs_f
for(unsigned int src = 0; src < 3; ++src) {
for(unsigned int chan = 0; chan < 4; ++chan) {
if (!GET_BIT(srcmasks[src], chan))
SET_SWZ(inst->I.SrcReg[src].Swizzle, chan, RC_SWIZZLE_UNUSED);
SET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan, RC_SWIZZLE_UNUSED);
}
}
}

40
src/mesa/drivers/dri/r300/compiler/radeon_dataflow_swizzles.c
View File

@ -40,48 +40,48 @@ static void rewrite_source(struct radeon_compiler * c,
usemask = 0;
for(unsigned int chan = 0; chan < 4; ++chan) {
if (GET_SWZ(inst->I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED)
if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED)
usemask |= 1 << chan;
}
c->SwizzleCaps->Split(inst->I.SrcReg[src], usemask, &split);
c->SwizzleCaps->Split(inst->U.I.SrcReg[src], usemask, &split);
for(unsigned int phase = 0; phase < split.NumPhases; ++phase) {
struct rc_instruction * mov = rc_insert_new_instruction(c, inst->Prev);
unsigned int phase_refmask;
unsigned int masked_negate;
mov->I.Opcode = RC_OPCODE_MOV;
mov->I.DstReg.File = RC_FILE_TEMPORARY;
mov->I.DstReg.Index = tempreg;
mov->I.DstReg.WriteMask = split.Phase[phase];
mov->I.SrcReg[0] = inst->I.SrcReg[src];
mov->U.I.Opcode = RC_OPCODE_MOV;
mov->U.I.DstReg.File = RC_FILE_TEMPORARY;
mov->U.I.DstReg.Index = tempreg;
mov->U.I.DstReg.WriteMask = split.Phase[phase];
mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src];
phase_refmask = 0;
for(unsigned int chan = 0; chan < 4; ++chan) {
if (!GET_BIT(split.Phase[phase], chan))
SET_SWZ(mov->I.SrcReg[0].Swizzle, chan, RC_SWIZZLE_UNUSED);
SET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan, RC_SWIZZLE_UNUSED);
else
phase_refmask |= 1 << GET_SWZ(mov->I.SrcReg[0].Swizzle, chan);
phase_refmask |= 1 << GET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan);
}
phase_refmask &= RC_MASK_XYZW;
masked_negate = split.Phase[phase] & mov->I.SrcReg[0].Negate;
masked_negate = split.Phase[phase] & mov->U.I.SrcReg[0].Negate;
if (masked_negate == 0)
mov->I.SrcReg[0].Negate = 0;
mov->U.I.SrcReg[0].Negate = 0;
else if (masked_negate == split.Phase[phase])
mov->I.SrcReg[0].Negate = RC_MASK_XYZW;
mov->U.I.SrcReg[0].Negate = RC_MASK_XYZW;
}
inst->I.SrcReg[src].File = RC_FILE_TEMPORARY;
inst->I.SrcReg[src].Index = tempreg;
inst->I.SrcReg[src].Swizzle = 0;
inst->I.SrcReg[src].Negate = RC_MASK_NONE;
inst->I.SrcReg[src].Abs = 0;
inst->U.I.SrcReg[src].File = RC_FILE_TEMPORARY;
inst->U.I.SrcReg[src].Index = tempreg;
inst->U.I.SrcReg[src].Swizzle = 0;
inst->U.I.SrcReg[src].Negate = RC_MASK_NONE;
inst->U.I.SrcReg[src].Abs = 0;
for(unsigned int chan = 0; chan < 4; ++chan) {
SET_SWZ(inst->I.SrcReg[src].Swizzle, chan,
SET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan,
GET_BIT(usemask, chan) ? chan : RC_SWIZZLE_UNUSED);
}
}
@ -91,11 +91,11 @@ void rc_dataflow_swizzles(struct radeon_compiler * c)
struct rc_instruction * inst;
for(inst = c->Program.Instructions.Next; inst != &c->Program.Instructions; inst = inst->Next) {
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
unsigned int src;
for(src = 0; src < opcode->NumSrcRegs; ++src) {
if (!c->SwizzleCaps->IsNative(inst->I.Opcode, inst->I.SrcReg[src]))
if (!c->SwizzleCaps->IsNative(inst->U.I.Opcode, inst->U.I.SrcReg[src]))
rewrite_source(c, inst, src);
}
}

12
src/mesa/drivers/dri/r300/compiler/radeon_program.c
View File

@ -98,7 +98,7 @@ unsigned int rc_find_free_temporary(struct radeon_compiler * c)
memset(used, 0, sizeof(used));
for (struct rc_instruction * rcinst = c->Program.Instructions.Next; rcinst != &c->Program.Instructions; rcinst = rcinst->Next) {
const struct rc_sub_instruction *inst = &rcinst->I;
const struct rc_sub_instruction *inst = &rcinst->U.I;
const struct rc_opcode_info *opcode = rc_get_opcode_info(inst->Opcode);
unsigned int k;
@ -129,11 +129,11 @@ struct rc_instruction *rc_alloc_instruction(struct radeon_compiler * c)
memset(inst, 0, sizeof(struct rc_instruction));
inst->I.Opcode = RC_OPCODE_ILLEGAL_OPCODE;
inst->I.DstReg.WriteMask = RC_MASK_XYZW;
inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
inst->I.SrcReg[1].Swizzle = RC_SWIZZLE_XYZW;
inst->I.SrcReg[2].Swizzle = RC_SWIZZLE_XYZW;
inst->U.I.Opcode = RC_OPCODE_ILLEGAL_OPCODE;
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZW;
inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_XYZW;
inst->U.I.SrcReg[2].Swizzle = RC_SWIZZLE_XYZW;
return inst;
}

10
src/mesa/drivers/dri/r300/compiler/radeon_program.h
View File

@ -109,11 +109,19 @@ struct rc_sub_instruction {
/*@}*/
};
typedef enum {
RC_INSTRUCTION_NORMAL = 0,
RC_INSTRUCTION_PAIR
} rc_instruction_type;
struct rc_instruction {
struct rc_instruction * Prev;
struct rc_instruction * Next;
struct rc_sub_instruction I;
rc_instruction_type Type;
union {
struct rc_sub_instruction I;
} U;
/**
* Warning: IPs are not stable. If you want to use them,

186
src/mesa/drivers/dri/r300/compiler/radeon_program_alu.c
View File

@ -45,10 +45,10 @@ static struct rc_instruction *emit1(
{
struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
fpi->I.Opcode = Opcode;
fpi->I.SaturateMode = Saturate;
fpi->I.DstReg = DstReg;
fpi->I.SrcReg[0] = SrcReg;
fpi->U.I.Opcode = Opcode;
fpi->U.I.SaturateMode = Saturate;
fpi->U.I.DstReg = DstReg;
fpi->U.I.SrcReg[0] = SrcReg;
return fpi;
}
@ -59,11 +59,11 @@ static struct rc_instruction *emit2(
{
struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
fpi->I.Opcode = Opcode;
fpi->I.SaturateMode = Saturate;
fpi->I.DstReg = DstReg;
fpi->I.SrcReg[0] = SrcReg0;
fpi->I.SrcReg[1] = SrcReg1;
fpi->U.I.Opcode = Opcode;
fpi->U.I.SaturateMode = Saturate;
fpi->U.I.DstReg = DstReg;
fpi->U.I.SrcReg[0] = SrcReg0;
fpi->U.I.SrcReg[1] = SrcReg1;
return fpi;
}
@ -75,12 +75,12 @@ static struct rc_instruction *emit3(
{
struct rc_instruction *fpi = rc_insert_new_instruction(c, after);
fpi->I.Opcode = Opcode;
fpi->I.SaturateMode = Saturate;
fpi->I.DstReg = DstReg;
fpi->I.SrcReg[0] = SrcReg0;
fpi->I.SrcReg[1] = SrcReg1;
fpi->I.SrcReg[2] = SrcReg2;
fpi->U.I.Opcode = Opcode;
fpi->U.I.SaturateMode = Saturate;
fpi->U.I.DstReg = DstReg;
fpi->U.I.SrcReg[0] = SrcReg0;
fpi->U.I.SrcReg[1] = SrcReg1;
fpi->U.I.SrcReg[2] = SrcReg2;
return fpi;
}
@ -168,36 +168,36 @@ static struct rc_src_register scalar(struct rc_src_register reg)
static void transform_ABS(struct radeon_compiler* c,
struct rc_instruction* inst)
{
struct rc_src_register src = inst->I.SrcReg[0];
struct rc_src_register src = inst->U.I.SrcReg[0];
src.Abs = 1;
src.Negate = RC_MASK_NONE;
emit1(c, inst->Prev, RC_OPCODE_MOV, inst->I.SaturateMode, inst->I.DstReg, src);
emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode, inst->U.I.DstReg, src);
rc_remove_instruction(inst);
}
static void transform_DP3(struct radeon_compiler* c,
struct rc_instruction* inst)
{
struct rc_src_register src0 = inst->I.SrcReg[0];
struct rc_src_register src1 = inst->I.SrcReg[1];
struct rc_src_register src0 = inst->U.I.SrcReg[0];
struct rc_src_register src1 = inst->U.I.SrcReg[1];
src0.Negate &= ~RC_MASK_W;
src0.Swizzle &= ~(7 << (3 * 3));
src0.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
src1.Negate &= ~RC_MASK_W;
src1.Swizzle &= ~(7 << (3 * 3));
src1.Swizzle |= RC_SWIZZLE_ZERO << (3 * 3);
emit2(c, inst->Prev, RC_OPCODE_DP4, inst->I.SaturateMode, inst->I.DstReg, src0, src1);
emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, src1);
rc_remove_instruction(inst);
}
static void transform_DPH(struct radeon_compiler* c,
struct rc_instruction* inst)
{
struct rc_src_register src0 = inst->I.SrcReg[0];
struct rc_src_register src0 = inst->U.I.SrcReg[0];
src0.Negate &= ~RC_MASK_W;
src0.Swizzle &= ~(7 << (3 * 3));
src0.Swizzle |= RC_SWIZZLE_ONE << (3 * 3);
emit2(c, inst->Prev, RC_OPCODE_DP4, inst->I.SaturateMode, inst->I.DstReg, src0, inst->I.SrcReg[1]);
emit2(c, inst->Prev, RC_OPCODE_DP4, inst->U.I.SaturateMode, inst->U.I.DstReg, src0, inst->U.I.SrcReg[1]);
rc_remove_instruction(inst);
}
@ -208,9 +208,9 @@ static void transform_DPH(struct radeon_compiler* c,
static void transform_DST(struct radeon_compiler* c,
struct rc_instruction* inst)
{
emit2(c, inst->Prev, RC_OPCODE_MUL, inst->I.SaturateMode, inst->I.DstReg,
swizzle(inst->I.SrcReg[0], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ONE),
swizzle(inst->I.SrcReg[1], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_ONE, RC_SWIZZLE_W));
emit2(c, inst->Prev, RC_OPCODE_MUL, inst->U.I.SaturateMode, inst->U.I.DstReg,
swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_ONE),
swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_ONE, RC_SWIZZLE_Y, RC_SWIZZLE_ONE, RC_SWIZZLE_W));
rc_remove_instruction(inst);
}
@ -218,9 +218,9 @@ static void transform_FLR(struct radeon_compiler* c,
struct rc_instruction* inst)
{
int tempreg = rc_find_free_temporary(c);
emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->I.SrcReg[0]);
emit2(c, inst->Prev, RC_OPCODE_ADD, inst->I.SaturateMode, inst->I.DstReg,
inst->I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, tempreg)));
emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0]);
emit2(c, inst->Prev, RC_OPCODE_ADD, inst->U.I.SaturateMode, inst->U.I.DstReg,
inst->U.I.SrcReg[0], negate(srcreg(RC_FILE_TEMPORARY, tempreg)));
rc_remove_instruction(inst);
}
@ -252,19 +252,19 @@ static void transform_LIT(struct radeon_compiler* c,
constant = rc_constants_add_immediate_scalar(&c->Program.Constants, -127.999999, &constant_swizzle);
if (inst->I.DstReg.WriteMask != RC_MASK_XYZW || inst->I.DstReg.File != RC_FILE_TEMPORARY) {
if (inst->U.I.DstReg.WriteMask != RC_MASK_XYZW || inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
struct rc_instruction * inst_mov;
inst_mov = emit1(c, inst,
RC_OPCODE_MOV, 0, inst->I.DstReg,
RC_OPCODE_MOV, 0, inst->U.I.DstReg,
srcreg(RC_FILE_TEMPORARY, rc_find_free_temporary(c)));
inst->I.DstReg.File = RC_FILE_TEMPORARY;
inst->I.DstReg.Index = inst_mov->I.SrcReg[0].Index;
inst->I.DstReg.WriteMask = RC_MASK_XYZW;
inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst->U.I.DstReg.Index = inst_mov->U.I.SrcReg[0].Index;
inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
}
temp = inst->I.DstReg.Index;
temp = inst->U.I.DstReg.Index;
srctemp = srcreg(RC_FILE_TEMPORARY, temp);
// tmp.x = max(0.0, Src.x);
@ -272,7 +272,7 @@ static void transform_LIT(struct radeon_compiler* c,
// tmp.w = clamp(Src.z, -128+eps, 128-eps);
emit2(c, inst->Prev, RC_OPCODE_MAX, 0,
dstregtmpmask(temp, RC_MASK_XYW),
inst->I.SrcReg[0],
inst->U.I.SrcReg[0],
swizzle(srcreg(RC_FILE_CONSTANT, constant),
RC_SWIZZLE_ZERO, RC_SWIZZLE_ZERO, RC_SWIZZLE_ZERO, constant_swizzle&3));
emit2(c, inst->Prev, RC_OPCODE_MIN, 0,
@ -293,14 +293,14 @@ static void transform_LIT(struct radeon_compiler* c,
swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W));
// tmp.z = (tmp.x > 0) ? tmp.w : 0.0
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->I.SaturateMode,
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode,
dstregtmpmask(temp, RC_MASK_Z),
negate(swizzle(srctemp, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X)),
swizzle(srctemp, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
builtin_zero);
// tmp.x, tmp.y, tmp.w = 1.0, tmp.x, 1.0
emit1(c, inst->Prev, RC_OPCODE_MOV, inst->I.SaturateMode,
emit1(c, inst->Prev, RC_OPCODE_MOV, inst->U.I.SaturateMode,
dstregtmpmask(temp, RC_MASK_XYW),
swizzle(srctemp, RC_SWIZZLE_ONE, RC_SWIZZLE_X, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE));
@ -314,10 +314,10 @@ static void transform_LRP(struct radeon_compiler* c,
emit2(c, inst->Prev, RC_OPCODE_ADD, 0,
dstreg(RC_FILE_TEMPORARY, tempreg),
inst->I.SrcReg[1], negate(inst->I.SrcReg[2]));
emit3(c, inst->Prev, RC_OPCODE_MAD, inst->I.SaturateMode,
inst->I.DstReg,
inst->I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, tempreg), inst->I.SrcReg[2]);
inst->U.I.SrcReg[1], negate(inst->U.I.SrcReg[2]));
emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode,
inst->U.I.DstReg,
inst->U.I.SrcReg[0], srcreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[2]);
rc_remove_instruction(inst);
}
@ -331,9 +331,9 @@ static void transform_POW(struct radeon_compiler* c,
tempdst.WriteMask = RC_MASK_W;
tempsrc.Swizzle = RC_SWIZZLE_WWWW;
emit1(c, inst->Prev, RC_OPCODE_LG2, 0, tempdst, scalar(inst->I.SrcReg[0]));
emit2(c, inst->Prev, RC_OPCODE_MUL, 0, tempdst, tempsrc, scalar(inst->I.SrcReg[1]));
emit1(c, inst->Prev, RC_OPCODE_EX2, inst->I.SaturateMode, inst->I.DstReg, tempsrc);
emit1(c, inst->Prev, RC_OPCODE_LG2, 0, tempdst, scalar(inst->U.I.SrcReg[0]));
emit2(c, inst->Prev, RC_OPCODE_MUL, 0, tempdst, tempsrc, scalar(inst->U.I.SrcReg[1]));
emit1(c, inst->Prev, RC_OPCODE_EX2, inst->U.I.SaturateMode, inst->U.I.DstReg, tempsrc);
rc_remove_instruction(inst);
}
@ -341,7 +341,7 @@ static void transform_POW(struct radeon_compiler* c,
static void transform_RSQ(struct radeon_compiler* c,
struct rc_instruction* inst)
{
inst->I.SrcReg[0] = absolute(inst->I.SrcReg[0]);
inst->U.I.SrcReg[0] = absolute(inst->U.I.SrcReg[0]);
}
static void transform_SGE(struct radeon_compiler* c,
@ -349,8 +349,8 @@ static void transform_SGE(struct radeon_compiler* c,
{
int tempreg = rc_find_free_temporary(c);
emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->I.SrcReg[0], negate(inst->I.SrcReg[1]));
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->I.SaturateMode, inst->I.DstReg,
emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
srcreg(RC_FILE_TEMPORARY, tempreg), builtin_zero, builtin_one);
rc_remove_instruction(inst);
@ -361,8 +361,8 @@ static void transform_SLT(struct radeon_compiler* c,
{
int tempreg = rc_find_free_temporary(c);
emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->I.SrcReg[0], negate(inst->I.SrcReg[1]));
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->I.SaturateMode, inst->I.DstReg,
emit2(c, inst->Prev, RC_OPCODE_ADD, 0, dstreg(RC_FILE_TEMPORARY, tempreg), inst->U.I.SrcReg[0], negate(inst->U.I.SrcReg[1]));
emit3(c, inst->Prev, RC_OPCODE_CMP, inst->U.I.SaturateMode, inst->U.I.DstReg,
srcreg(RC_FILE_TEMPORARY, tempreg), builtin_one, builtin_zero);
rc_remove_instruction(inst);
@ -371,14 +371,14 @@ static void transform_SLT(struct radeon_compiler* c,
static void transform_SUB(struct radeon_compiler* c,
struct rc_instruction* inst)
{
inst->I.Opcode = RC_OPCODE_ADD;
inst->I.SrcReg[1] = negate(inst->I.SrcReg[1]);
inst->U.I.Opcode = RC_OPCODE_ADD;
inst->U.I.SrcReg[1] = negate(inst->U.I.SrcReg[1]);
}
static void transform_SWZ(struct radeon_compiler* c,
struct rc_instruction* inst)
{
inst->I.Opcode = RC_OPCODE_MOV;
inst->U.I.Opcode = RC_OPCODE_MOV;
}
static void transform_XPD(struct radeon_compiler* c,
@ -387,11 +387,11 @@ static void transform_XPD(struct radeon_compiler* c,
int tempreg = rc_find_free_temporary(c);
emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dstreg(RC_FILE_TEMPORARY, tempreg),
swizzle(inst->I.SrcReg[0], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
swizzle(inst->I.SrcReg[1], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W));
emit3(c, inst->Prev, RC_OPCODE_MAD, inst->I.SaturateMode, inst->I.DstReg,
swizzle(inst->I.SrcReg[0], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W),
swizzle(inst->I.SrcReg[1], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W));
emit3(c, inst->Prev, RC_OPCODE_MAD, inst->U.I.SaturateMode, inst->U.I.DstReg,
swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_W),
swizzle(inst->U.I.SrcReg[1], RC_SWIZZLE_Z, RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_W),
negate(srcreg(RC_FILE_TEMPORARY, tempreg)));
rc_remove_instruction(inst);
@ -417,7 +417,7 @@ int radeonTransformALU(
struct rc_instruction* inst,
void* unused)
{
switch(inst->I.Opcode) {
switch(inst->U.I.Opcode) {
case RC_OPCODE_ABS: transform_ABS(c, inst); return 1;
case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
case RC_OPCODE_DST: transform_DST(c, inst); return 1;
@ -441,9 +441,9 @@ static void transform_r300_vertex_ABS(struct radeon_compiler* c,
struct rc_instruction* inst)
{
/* Note: r500 can take absolute values, but r300 cannot. */
inst->I.Opcode = RC_OPCODE_MAX;
inst->I.SrcReg[1] = inst->I.SrcReg[0];
inst->I.SrcReg[1].Negate ^= RC_MASK_XYZW;
inst->U.I.Opcode = RC_OPCODE_MAX;
inst->U.I.SrcReg[1] = inst->U.I.SrcReg[0];
inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
}
/**
@ -455,7 +455,7 @@ int r300_transform_vertex_alu(
struct rc_instruction* inst,
void* unused)
{
switch(inst->I.Opcode) {
switch(inst->U.I.Opcode) {
case RC_OPCODE_ABS: transform_r300_vertex_ABS(c, inst); return 1;
case RC_OPCODE_DP3: transform_DP3(c, inst); return 1;
case RC_OPCODE_DPH: transform_DPH(c, inst); return 1;
@ -531,9 +531,9 @@ int radeonTransformTrigSimple(struct radeon_compiler* c,
struct rc_instruction* inst,
void* unused)
{
if (inst->I.Opcode != RC_OPCODE_COS &&
inst->I.Opcode != RC_OPCODE_SIN &&
inst->I.Opcode != RC_OPCODE_SCS)
if (inst->U.I.Opcode != RC_OPCODE_COS &&
inst->U.I.Opcode != RC_OPCODE_SIN &&
inst->U.I.Opcode != RC_OPCODE_SCS)
return 0;
unsigned int constants[2];
@ -541,12 +541,12 @@ int radeonTransformTrigSimple(struct radeon_compiler* c,
sincos_constants(c, constants);
if (inst->I.Opcode == RC_OPCODE_COS) {
if (inst->U.I.Opcode == RC_OPCODE_COS) {
// MAD tmp.x, src, 1/(2*PI), 0.75
// FRC tmp.x, tmp.x
// MAD tmp.z, tmp.x, 2*PI, -PI
emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W),
swizzle(inst->I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z),
swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X));
emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(tempreg, RC_MASK_W),
@ -556,12 +556,12 @@ int radeonTransformTrigSimple(struct radeon_compiler* c,
swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
sin_approx(c, inst, inst->I.DstReg,
sin_approx(c, inst, inst->U.I.DstReg,
swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
constants);
} else if (inst->I.Opcode == RC_OPCODE_SIN) {
} else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_W),
swizzle(inst->I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z),
swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y));
emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(tempreg, RC_MASK_W),
@ -571,12 +571,12 @@ int radeonTransformTrigSimple(struct radeon_compiler* c,
swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
sin_approx(c, inst, inst->I.DstReg,
sin_approx(c, inst, inst->U.I.DstReg,
swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
constants);
} else {
emit3(c, inst->Prev, RC_OPCODE_MAD, 0, dstregtmpmask(tempreg, RC_MASK_XY),
swizzle(inst->I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z),
swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_X, RC_SWIZZLE_Y, RC_SWIZZLE_Z, RC_SWIZZLE_W));
emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(tempreg, RC_MASK_XY),
@ -586,14 +586,14 @@ int radeonTransformTrigSimple(struct radeon_compiler* c,
swizzle(srcreg(RC_FILE_CONSTANT, constants[1]), RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W, RC_SWIZZLE_W),
negate(swizzle(srcreg(RC_FILE_CONSTANT, constants[0]), RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z, RC_SWIZZLE_Z)));
struct rc_dst_register dst = inst->I.DstReg;
struct rc_dst_register dst = inst->U.I.DstReg;
dst.WriteMask = inst->I.DstReg.WriteMask & RC_MASK_X;
dst.WriteMask = inst->U.I.DstReg.WriteMask & RC_MASK_X;
sin_approx(c, inst, dst,
swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
constants);
dst.WriteMask = inst->I.DstReg.WriteMask & RC_MASK_Y;
dst.WriteMask = inst->U.I.DstReg.WriteMask & RC_MASK_Y;
sin_approx(c, inst, dst,
swizzle(srcreg(RC_FILE_TEMPORARY, tempreg), RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y, RC_SWIZZLE_Y),
constants);
@ -617,9 +617,9 @@ int radeonTransformTrigScale(struct radeon_compiler* c,
struct rc_instruction* inst,
void* unused)
{
if (inst->I.Opcode != RC_OPCODE_COS &&
inst->I.Opcode != RC_OPCODE_SIN &&
inst->I.Opcode != RC_OPCODE_SCS)
if (inst->U.I.Opcode != RC_OPCODE_COS &&
inst->U.I.Opcode != RC_OPCODE_SIN &&
inst->U.I.Opcode != RC_OPCODE_SCS)
return 0;
static const float RCP_2PI = 0.15915494309189535;
@ -631,28 +631,28 @@ int radeonTransformTrigScale(struct radeon_compiler* c,
constant = rc_constants_add_immediate_scalar(&c->Program.Constants, RCP_2PI, &constant_swizzle);
emit2(c, inst->Prev, RC_OPCODE_MUL, 0, dstregtmpmask(temp, RC_MASK_W),
swizzle(inst->I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
swizzle(inst->U.I.SrcReg[0], RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X, RC_SWIZZLE_X),
srcregswz(RC_FILE_CONSTANT, constant, constant_swizzle));
emit1(c, inst->Prev, RC_OPCODE_FRC, 0, dstregtmpmask(temp, RC_MASK_W),
srcreg(RC_FILE_TEMPORARY, temp));
if (inst->I.Opcode == RC_OPCODE_COS) {
emit1(c, inst->Prev, RC_OPCODE_COS, inst->I.SaturateMode, inst->I.DstReg,
if (inst->U.I.Opcode == RC_OPCODE_COS) {
emit1(c, inst->Prev, RC_OPCODE_COS, inst->U.I.SaturateMode, inst->U.I.DstReg,
srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
} else if (inst->I.Opcode == RC_OPCODE_SIN) {
emit1(c, inst->Prev, RC_OPCODE_SIN, inst->I.SaturateMode,
inst->I.DstReg, srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
} else if (inst->I.Opcode == RC_OPCODE_SCS) {
struct rc_dst_register moddst = inst->I.DstReg;
} else if (inst->U.I.Opcode == RC_OPCODE_SIN) {
emit1(c, inst->Prev, RC_OPCODE_SIN, inst->U.I.SaturateMode,
inst->U.I.DstReg, srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
} else if (inst->U.I.Opcode == RC_OPCODE_SCS) {
struct rc_dst_register moddst = inst->U.I.DstReg;
if (inst->I.DstReg.WriteMask & RC_MASK_X) {
if (inst->U.I.DstReg.WriteMask & RC_MASK_X) {
moddst.WriteMask = RC_MASK_X;
emit1(c, inst->Prev, RC_OPCODE_COS, inst->I.SaturateMode, moddst,
emit1(c, inst->Prev, RC_OPCODE_COS, inst->U.I.SaturateMode, moddst,
srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
}
if (inst->I.DstReg.WriteMask & RC_MASK_Y) {
if (inst->U.I.DstReg.WriteMask & RC_MASK_Y) {
moddst.WriteMask = RC_MASK_Y;
emit1(c, inst->Prev, RC_OPCODE_SIN, inst->I.SaturateMode, moddst,
emit1(c, inst->Prev, RC_OPCODE_SIN, inst->U.I.SaturateMode, moddst,
srcregswz(RC_FILE_TEMPORARY, temp, RC_SWIZZLE_WWWW));
}
}
@ -674,11 +674,11 @@ int radeonTransformDeriv(struct radeon_compiler* c,
struct rc_instruction* inst,
void* unused)
{
if (inst->I.Opcode != RC_OPCODE_DDX && inst->I.Opcode != RC_OPCODE_DDY)
if (inst->U.I.Opcode != RC_OPCODE_DDX && inst->U.I.Opcode != RC_OPCODE_DDY)
return 0;
inst->I.SrcReg[1].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_ONE, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE);
inst->I.SrcReg[1].Negate = RC_MASK_XYZW;
inst->U.I.SrcReg[1].Swizzle = RC_MAKE_SWIZZLE(RC_SWIZZLE_ONE, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE, RC_SWIZZLE_ONE);
inst->U.I.SrcReg[1].Negate = RC_MASK_XYZW;
return 1;
}

2
src/mesa/drivers/dri/r300/compiler/radeon_program_pair.c
View File

@ -341,7 +341,7 @@ static void scan_instructions(struct pair_state *s)
struct pair_state_instruction *pairinst = memory_pool_malloc(&s->Compiler->Base.Pool, sizeof(*pairinst));
memset(pairinst, 0, sizeof(struct pair_state_instruction));
pairinst->Instruction = source->I;
pairinst->Instruction = source->U.I;
pairinst->IP = ip;
final_rewrite(s, &pairinst->Instruction);
classify_instruction(s, pairinst);

2
src/mesa/drivers/dri/r300/compiler/radeon_program_pair.h
View File

@ -28,8 +28,6 @@
#ifndef __RADEON_PROGRAM_PAIR_H_
#define __RADEON_PROGRAM_PAIR_H_
#include "radeon_program.h"
struct r300_fragment_program_compiler;

20
src/mesa/drivers/dri/r300/compiler/radeon_program_print.c
View File

@ -144,12 +144,12 @@ static void rc_print_src_register(FILE * f, struct rc_src_register src)
static void rc_print_instruction(FILE * f, struct rc_instruction * inst)
{
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->I.Opcode);
const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode);
unsigned int reg;
fprintf(f, "%s", opcode->Name);
switch(inst->I.SaturateMode) {
switch(inst->U.I.SaturateMode) {
case RC_SATURATE_NONE: break;
case RC_SATURATE_ZERO_ONE: fprintf(f, "_SAT"); break;
case RC_SATURATE_MINUS_PLUS_ONE: fprintf(f, "_SAT2"); break;
@ -158,7 +158,7 @@ static void rc_print_instruction(FILE * f, struct rc_instruction * inst)
if (opcode->HasDstReg) {
fprintf(f, " ");
rc_print_dst_register(f, inst->I.DstReg);
rc_print_dst_register(f, inst->U.I.DstReg);
if (opcode->NumSrcRegs)
fprintf(f, ",");
}
@ -167,23 +167,23 @@ static void rc_print_instruction(FILE * f, struct rc_instruction * inst)
if (reg > 0)
fprintf(f, ",");
fprintf(f, " ");
rc_print_src_register(f, inst->I.SrcReg[reg]);
rc_print_src_register(f, inst->U.I.SrcReg[reg]);
}
if (opcode->HasTexture) {
fprintf(f, ", %s%s[%u]",
textarget_to_string(inst->I.TexSrcTarget),
inst->I.TexShadow ? "SHADOW" : "",
inst->I.TexSrcUnit);
textarget_to_string(inst->U.I.TexSrcTarget),
inst->U.I.TexShadow ? "SHADOW" : "",
inst->U.I.TexSrcUnit);
}
fprintf(f, ";");
if (inst->I.WriteALUResult) {
if (inst->U.I.WriteALUResult) {
fprintf(f, " [aluresult = (");
rc_print_comparefunc(f,
(inst->I.WriteALUResult == RC_ALURESULT_X) ? "x" : "w",
inst->I.ALUResultCompare, "0");
(inst->U.I.WriteALUResult == RC_ALURESULT_X) ? "x" : "w",
inst->U.I.ALUResultCompare, "0");
fprintf(f, ")]");
}

22
src/mesa/drivers/dri/r300/r300_vertprog.c
View File

@ -217,20 +217,20 @@ static void initialize_NV_registers(struct radeon_compiler * compiler)
for(reg = 0; reg < 12; ++reg) {
inst = rc_insert_new_instruction(compiler, &compiler->Program.Instructions);
inst->I.Opcode = RC_OPCODE_MOV;
inst->I.DstReg.File = RC_FILE_TEMPORARY;
inst->I.DstReg.Index = reg;
inst->I.SrcReg[0].File = RC_FILE_NONE;
inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
inst->U.I.Opcode = RC_OPCODE_MOV;
inst->U.I.DstReg.File = RC_FILE_TEMPORARY;
inst->U.I.DstReg.Index = reg;
inst->U.I.SrcReg[0].File = RC_FILE_NONE;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
}
inst = rc_insert_new_instruction(compiler, &compiler->Program.Instructions);
inst->I.Opcode = RC_OPCODE_ARL;
inst->I.DstReg.File = RC_FILE_ADDRESS;
inst->I.DstReg.Index = 0;
inst->I.DstReg.WriteMask = WRITEMASK_X;
inst->I.SrcReg[0].File = RC_FILE_NONE;
inst->I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
inst->U.I.Opcode = RC_OPCODE_ARL;
inst->U.I.DstReg.File = RC_FILE_ADDRESS;
inst->U.I.DstReg.Index = 0;
inst->U.I.DstReg.WriteMask = WRITEMASK_X;
inst->U.I.SrcReg[0].File = RC_FILE_NONE;
inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000;
}
static struct r300_vertex_program *build_program(GLcontext *ctx,

18
src/mesa/drivers/dri/r300/radeon_mesa_to_rc.c
View File

@ -152,25 +152,25 @@ static void translate_instruction(struct radeon_compiler * c,
const struct rc_opcode_info * opcode;
unsigned int i;
dest->I.Opcode = translate_opcode(src->Opcode);
if (dest->I.Opcode == RC_OPCODE_ILLEGAL_OPCODE) {
dest->U.I.Opcode = translate_opcode(src->Opcode);
if (dest->U.I.Opcode == RC_OPCODE_ILLEGAL_OPCODE) {
rc_error(c, "Unsupported opcode %i\n", src->Opcode);
return;
}
dest->I.SaturateMode = translate_saturate(src->SaturateMode);
dest->U.I.SaturateMode = translate_saturate(src->SaturateMode);
opcode = rc_get_opcode_info(dest->I.Opcode);
opcode = rc_get_opcode_info(dest->U.I.Opcode);
for(i = 0; i < opcode->NumSrcRegs; ++i)
translate_srcreg(&dest->I.SrcReg[i], &src->SrcReg[i]);
translate_srcreg(&dest->U.I.SrcReg[i], &src->SrcReg[i]);
if (opcode->HasDstReg)
translate_dstreg(&dest->I.DstReg, &src->DstReg);
translate_dstreg(&dest->U.I.DstReg, &src->DstReg);
if (opcode->HasTexture) {
dest->I.TexSrcUnit = src->TexSrcUnit;
dest->I.TexSrcTarget = translate_tex_target(src->TexSrcTarget);
dest->I.TexShadow = src->TexShadow;
dest->U.I.TexSrcUnit = src->TexSrcUnit;
dest->U.I.TexSrcTarget = translate_tex_target(src->TexSrcTarget);
dest->U.I.TexShadow = src->TexShadow;
}
}