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gallium/radeon: clean up and better comment use_staging_texture 

Next commits will add other things around this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák 2016-05-18 03:06:04 +02:00
parent b033584299
commit 9927c8138a
1 changed files with 23 additions and 19 deletions
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42
src/gallium/drivers/radeon/r600_texture.c
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@ -1226,31 +1226,35 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
struct r600_common_context *rctx = (struct r600_common_context*)ctx; struct r600_common_context *rctx = (struct r600_common_context*)ctx;
struct r600_texture *rtex = (struct r600_texture*)texture; struct r600_texture *rtex = (struct r600_texture*)texture;
struct r600_transfer *trans; struct r600_transfer *trans;
boolean use_staging_texture = FALSE;
struct r600_resource *buf; struct r600_resource *buf;
unsigned offset = 0; unsigned offset = 0;
char *map; char *map;
bool use_staging_texture = false;
assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER)); assert(!(texture->flags & R600_RESOURCE_FLAG_TRANSFER));
/* We cannot map a tiled texture directly because the data is /* Depth textures use staging unconditionally. */
* in a different order, therefore we do detiling using a blit. if (!rtex->is_depth) {
* /* Tiled textures need to be converted into a linear texture for CPU
* Also, use a temporary in GTT memory for read transfers, as * access. The staging texture is always linear and is placed in GART.
* the CPU is much happier reading out of cached system memory *
* than uncached VRAM. * Reading from VRAM is slow, always use the staging texture in
*/ * this case.
if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) { *
use_staging_texture = TRUE; * Use the staging texture for uploads if the underlying BO
} else if ((usage & PIPE_TRANSFER_READ) && * is busy.
rtex->resource.domains & RADEON_DOMAIN_VRAM) { */
/* Untiled buffers in VRAM, which is slow for CPU reads */ if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D)
use_staging_texture = TRUE; use_staging_texture = true;
} else if (!(usage & PIPE_TRANSFER_READ) && else if (usage & PIPE_TRANSFER_READ)
(r600_rings_is_buffer_referenced(rctx, rtex->resource.buf, RADEON_USAGE_READWRITE) || use_staging_texture = (rtex->resource.domains &
!rctx->ws->buffer_wait(rtex->resource.buf, 0, RADEON_USAGE_READWRITE))) { RADEON_DOMAIN_VRAM) != 0;
/* Use a staging texture for uploads if the underlying BO is busy. */ /* Write & linear only: */
use_staging_texture = TRUE; else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
RADEON_USAGE_READWRITE) ||
!rctx->ws->buffer_wait(rtex->resource.buf, 0,
RADEON_USAGE_READWRITE))
use_staging_texture = true;
} }
trans = CALLOC_STRUCT(r600_transfer); trans = CALLOC_STRUCT(r600_transfer);