intel/eu: Clarify spec citations for XeHP region restrictions

When this rule started causing issues, I looked it up in the
documentation, and found the rule for 64-bit destinations and
integer DWord multiplication, but there was no mention of floating
point destinations, as the text in brackets suggested.  The actual
restriction text had been updated, so this led to some confusion
where I thought the conditions had been changed in newer docs.

However, what's actually going on is that there are two separate
conditions, each listed in separate rows of the table.  One lists
64-bit destinations or integer DWord multiplication, and the other
mentions floating-point destinations.  In both cases, the actual
restrictions are identical, so we handle them together in the code.

Try to update the comment to avoid future confusion.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17624>

src/intel/compiler/brw_eu_validate.c

@@ -1974,11 +1974,16 @@ special_requirements_for_handling_double_precision_data_types(
 
       /* From the hardware spec section "Register Region Restrictions":
        *
-       * "In case where source or destination datatype is 64b or operation is
-       *  integer DWord multiply [or in case where a floating point data type
-       *  is used as destination]:
+       * There are two rules:
        *
-       *   1. Register Regioning patterns where register data bit location
+       * "In case of all floating point data types used in destination:" and
+       *
+       * "In case where source or destination datatype is 64b or operation is
+       *  integer DWord multiply:"
+       *
+       * both of which list the same restrictions:
+       *
+       *  "1. Register Regioning patterns where register data bit location
        *      of the LSB of the channels are changed between source and
        *      destination are not supported on Src0 and Src1 except for
        *      broadcast of a scalar.