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radeonsi: add support for EXT_depth_bounds_test 

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2015-08-10 02:23:21 +02:00
parent 36a6f848bb
commit 97f58fb59a
3 changed files with 8 additions and 5 deletions
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1
docs/relnotes/11.0.0.html
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@ -58,6 +58,7 @@ Note: some of the new features are only available with certain drivers.
<li>GL_ARB_tessellation_shader on nvc0, radeonsi</li>
<li>GL_ARB_vertex_attrib_64bit on llvmpipe, radeonsi</li>
<li>GL_ARB_viewport_array on radeonsi</li>
<li>GL_EXT_depth_bounds_test on radeonsi, nv30, nv50, nvc0</li>
<li>GL_OES_texture_float on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe</li>
<li>GL_OES_texture_half_float on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe</li>
<li>GL_OES_texture_float_linear on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe</li>

2
src/gallium/drivers/radeonsi/si_pipe.c
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@ -259,6 +259,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
case PIPE_CAP_DEPTH_BOUNDS_TEST:
return 1;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@ -301,7 +302,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_VERTEXID_NOBASE:
case PIPE_CAP_DEPTH_BOUNDS_TEST:
return 0;
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:

10
src/gallium/drivers/radeonsi/si_state.c
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@ -838,7 +838,8 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
S_028800_ZFUNC(state->depth.func);
S_028800_ZFUNC(state->depth.func) |
S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
/* stencil */
if (state->stencil[0].enabled) {
@ -867,9 +868,12 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
dsa->alpha_func = PIPE_FUNC_ALWAYS;
}
/* misc */
si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
if (state->depth.bounds_test) {
si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
}
return dsa;
}
@ -3230,8 +3234,6 @@ static void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0);
si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0);
si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);