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intel: Remove GEN_IS_HASWELL macro 

Use GEN_VERSIONx10 == 75 check in place of GEN_IS_HASWELL macro.
GEN_GEN and GEN_VERSIONx10 macros provide a consistent way to do platform
version checks. We can avoid platform specific macros.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9608>
This commit is contained in:
Anuj Phogat 2021-03-04 15:09:42 -08:00 committed by Marge Bot
parent 739486de2f
commit 97d6ceaf04
13 changed files with 91 additions and 92 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/intel/blorp/blorp_genX_exec.h
View File

@ -227,7 +227,7 @@ emit_urb_config(struct blorp_batch *batch,
false, false, entry_size,
entries, start, deref_block_size, &constrained);
#if GEN_GEN == 7 && !GEN_IS_HASWELL
#if GEN_GEN == 7 && GEN_VERSIONx10 != 75
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
*
* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
@ -958,7 +958,7 @@ blorp_emit_ps_config(struct blorp_batch *batch,
ps.MaximumNumberofThreads =
batch->blorp->isl_dev->info->max_wm_threads - 1;
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
ps.SampleMask = 1;
#endif

42
src/intel/common/mi_builder.h
View File

@ -95,7 +95,7 @@ struct mi_value {
uint32_t reg;
};
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
bool invert;
#endif
};
@ -130,7 +130,7 @@ mi_adjust_reg_num(uint32_t reg)
struct mi_builder {
__gen_user_data *user_data;
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
uint32_t gprs;
uint8_t gpr_refs[MI_BUILDER_NUM_ALLOC_GPRS];
@ -145,7 +145,7 @@ mi_builder_init(struct mi_builder *b, __gen_user_data *user_data)
memset(b, 0, sizeof(*b));
b->user_data = user_data;
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
b->gprs = 0;
b->num_math_dwords = 0;
#endif
@ -154,7 +154,7 @@ mi_builder_init(struct mi_builder *b, __gen_user_data *user_data)
static inline void
mi_builder_flush_math(struct mi_builder *b)
{
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
if (b->num_math_dwords == 0)
return;
@ -172,7 +172,7 @@ mi_builder_flush_math(struct mi_builder *b)
/* The actual hardware limit on GPRs */
#define _MI_BUILDER_NUM_HW_GPRS 16
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
static inline bool
mi_value_is_reg(struct mi_value val)
@ -221,7 +221,7 @@ mi_new_gpr(struct mi_builder *b)
.reg = _MI_BUILDER_GPR_BASE + gpr * 8,
};
}
#endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
#endif /* GEN_GEN >= 8 || GEN_VERSIONx10 == 75 */
/** Take a reference to a mi_value
*
@ -236,7 +236,7 @@ mi_new_gpr(struct mi_builder *b)
static inline struct mi_value
mi_value_ref(struct mi_builder *b, struct mi_value val)
{
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
if (_mi_value_is_allocated_gpr(val)) {
unsigned gpr = _mi_value_as_gpr(val);
assert(gpr < MI_BUILDER_NUM_ALLOC_GPRS);
@ -244,7 +244,7 @@ mi_value_ref(struct mi_builder *b, struct mi_value val)
assert(b->gpr_refs[gpr] < UINT8_MAX);
b->gpr_refs[gpr]++;
}
#endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
#endif /* GEN_GEN >= 8 || GEN_VERSIONx10 == 75 */
return val;
}
@ -256,7 +256,7 @@ mi_value_ref(struct mi_builder *b, struct mi_value val)
static inline void
mi_value_unref(struct mi_builder *b, struct mi_value val)
{
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
if (_mi_value_is_allocated_gpr(val)) {
unsigned gpr = _mi_value_as_gpr(val);
assert(gpr < MI_BUILDER_NUM_ALLOC_GPRS);
@ -265,7 +265,7 @@ mi_value_unref(struct mi_builder *b, struct mi_value val)
if (--b->gpr_refs[gpr] == 0)
b->gprs &= ~(1u << gpr);
}
#endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
#endif /* GEN_GEN >= 8 || GEN_VERSIONx10 == 75 */
}
static inline struct mi_value
@ -284,7 +284,7 @@ mi_reg32(uint32_t reg)
.type = MI_VALUE_TYPE_REG32,
.reg = reg,
};
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
assert(!_mi_value_is_allocated_gpr(val));
#endif
return val;
@ -297,7 +297,7 @@ mi_reg64(uint32_t reg)
.type = MI_VALUE_TYPE_REG64,
.reg = reg,
};
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
assert(!_mi_value_is_allocated_gpr(val));
#endif
return val;
@ -360,7 +360,7 @@ static inline void
_mi_copy_no_unref(struct mi_builder *b,
struct mi_value dst, struct mi_value src)
{
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
/* TODO: We could handle src.invert by emitting a bit of math if we really
* wanted to.
*/
@ -450,7 +450,7 @@ _mi_copy_no_unref(struct mi_builder *b,
cmm.DestinationMemoryAddress = dst.addr;
cmm.SourceMemoryAddress = src.addr;
}
#elif GEN_IS_HASWELL
#elif GEN_VERSIONx10 == 75
{
struct mi_value tmp = mi_new_gpr(b);
_mi_copy_no_unref(b, tmp, src);
@ -506,7 +506,7 @@ _mi_copy_no_unref(struct mi_builder *b,
case MI_VALUE_TYPE_REG32:
case MI_VALUE_TYPE_REG64:
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
if (src.reg != dst.reg) {
mi_builder_emit(b, GENX(MI_LOAD_REGISTER_REG), lrr) {
struct mi_reg_num reg = mi_adjust_reg_num(src.reg);
@ -536,7 +536,7 @@ _mi_copy_no_unref(struct mi_builder *b,
}
}
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
static inline struct mi_value
mi_resolve_invert(struct mi_builder *b, struct mi_value src);
#endif
@ -552,7 +552,7 @@ mi_resolve_invert(struct mi_builder *b, struct mi_value src);
static inline void
mi_store(struct mi_builder *b, struct mi_value dst, struct mi_value src)
{
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
src = mi_resolve_invert(b, src);
#endif
_mi_copy_no_unref(b, dst, src);
@ -564,7 +564,7 @@ static inline void
mi_memset(struct mi_builder *b, __gen_address_type dst,
uint32_t value, uint32_t size)
{
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
assert(b->num_math_dwords == 0);
#endif
@ -582,7 +582,7 @@ static inline void
mi_memcpy(struct mi_builder *b, __gen_address_type dst,
__gen_address_type src, uint32_t size)
{
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
assert(b->num_math_dwords == 0);
#endif
@ -592,7 +592,7 @@ mi_memcpy(struct mi_builder *b, __gen_address_type dst,
for (uint32_t i = 0; i < size; i += 4) {
struct mi_value dst_val = mi_mem32(__gen_address_offset(dst, i));
struct mi_value src_val = mi_mem32(__gen_address_offset(src, i));
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
mi_store(b, dst_val, src_val);
#else
/* IVB does not have a general purpose register for command streamer
@ -609,7 +609,7 @@ mi_memcpy(struct mi_builder *b, __gen_address_type dst,
* MI_MATH Section. Only available on Haswell+
*/
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
/**
* Perform a predicated store (assuming the condition is already loaded

10
src/intel/common/tests/mi_builder_test.cpp
View File

@ -55,7 +55,7 @@ __gen_address_offset(address addr, uint64_t offset)
return addr;
}
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
#define RSVD_TEMP_REG 0x2678 /* MI_ALU_REG15 */
#else
#define RSVD_TEMP_REG 0x2430 /* GEN7_3DPRIM_START_VERTEX */
@ -194,7 +194,7 @@ mi_builder_test::SetUp()
(void *)&getparam), 0) << strerror(errno);
ASSERT_TRUE(gen_get_device_info_from_pci_id(device_id, &devinfo));
if (devinfo.gen != GEN_GEN || devinfo.is_haswell != GEN_IS_HASWELL) {
if (devinfo.gen != GEN_GEN || devinfo.is_haswell != (GEN_VERSIONx10 == 75)) {
close(fd);
fd = -1;
continue;
@ -412,7 +412,7 @@ TEST_F(mi_builder_test, imm_mem)
}
/* mem -> mem copies are only supported on HSW+ */
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
TEST_F(mi_builder_test, mem_mem)
{
const uint64_t value = 0x0123456789abcdef;
@ -532,7 +532,7 @@ TEST_F(mi_builder_test, memcpy)
}
/* Start of MI_MATH section */
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
#define EXPECT_EQ_IMM(x, imm) EXPECT_EQ(x, mi_value_to_u64(imm))
@ -953,7 +953,7 @@ TEST_F(mi_builder_test, store_if)
EXPECT_EQ(*(uint32_t *)(output + 12), (uint32_t)canary);
}
#endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
#endif /* GEN_GEN >= 8 || GEN_VERSIONx10 == 75 */
#if GEN_VERSIONx10 >= 125

5
src/intel/genxml/gen_macros.h
View File

@ -31,7 +31,7 @@
*
* You can do pseudo-runtime checks in your function such as
*
* if (GEN_GEN > 8 || GEN_IS_HASWELL) {
* if (GEN_GEN > 8 || GEN_VERSIONx10 == 75) {
* // Do something
* }
*
@ -41,7 +41,7 @@
* For places where you really do have a compile-time conflict, you can
* use preprocessor logic:
*
* #if (GEN_GEN > 8 || GEN_IS_HASWELL)
* #if (GEN_GEN > 8 || GEN_VERSIONx10 == 75)
* // Do something
* #endif
*
@ -57,7 +57,6 @@
#endif
#define GEN_GEN ((GEN_VERSIONx10) / 10)
#define GEN_IS_HASWELL ((GEN_VERSIONx10) == 75)
#define GEN_IS_G4X ((GEN_VERSIONx10) == 45)
/* Prefixing macros */

2
src/intel/isl/isl_emit_depth_stencil.c
View File

@ -169,7 +169,7 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
sb.StencilCompressionEnable =
info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
#elif GEN_GEN >= 8 || GEN_IS_HASWELL
#elif GEN_GEN >= 8 || GEN_VERSIONx10 == 75
sb.StencilBufferEnable = true;
#endif
sb.SurfaceBaseAddress = info->stencil_address;

8
src/intel/isl/isl_surface_state.c
View File

@ -324,7 +324,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
assert(info->write_disables == 0);
#endif
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
s.IntegerSurfaceFormat =
isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
#endif
@ -363,7 +363,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
*
* This restriction appears to exist only on Ivy Bridge.
*/
if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
if (GEN_GEN == 7 && GEN_VERSIONx10 != 75 && !ISL_DEV_IS_BAYTRAIL(dev) &&
(info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
info->surf->samples > 1)
assert(info->view->base_array_layer == 0);
@ -529,7 +529,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
#endif
#endif
#if (GEN_GEN >= 8 || GEN_IS_HASWELL)
#if (GEN_GEN >= 8 || GEN_VERSIONx10 == 75)
if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
@ -917,7 +917,7 @@ isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
s.MOCS = info->mocs;
#endif
#if (GEN_GEN >= 8 || GEN_IS_HASWELL)
#if (GEN_GEN >= 8 || GEN_VERSIONx10 == 75)
s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;

8
src/intel/vulkan/gen7_cmd_buffer.c
View File

@ -33,7 +33,7 @@
#include "genxml/gen_macros.h"
#include "genxml/genX_pack.h"
#if GEN_GEN == 7 && !GEN_IS_HASWELL
#if GEN_GEN == 7 && GEN_VERSIONx10 != 75
static int64_t
clamp_int64(int64_t x, int64_t min, int64_t max)
{
@ -163,7 +163,7 @@ void genX(CmdBindIndexBuffer)(
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
if (GEN_IS_HASWELL)
if (GEN_VERSIONx10 == 75)
cmd_buffer->state.restart_index = restart_index_for_type(indexType);
cmd_buffer->state.gfx.gen7.index_buffer = buffer;
cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type(indexType);
@ -312,7 +312,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer;
uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset;
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
vf.CutIndex = cmd_buffer->state.restart_index;
@ -320,7 +320,7 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
#endif
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
#if !GEN_IS_HASWELL
#if GEN_VERSIONx10 != 75
ib.CutIndexEnable = pipeline->primitive_restart;
#endif
ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type;

40
src/intel/vulkan/genX_cmd_buffer.c
View File

@ -759,7 +759,7 @@ set_image_fast_clear_state(struct anv_cmd_buffer *cmd_buffer,
/* This is only really practical on haswell and above because it requires
* MI math in order to get it correct.
*/
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
static void
anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
@ -840,7 +840,7 @@ anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
mip.CompareOperation = COMPARE_SRCS_EQUAL;
}
}
#endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
#endif /* GEN_GEN >= 8 || GEN_VERSIONx10 == 75 */
#if GEN_GEN <= 8
static void
@ -931,7 +931,7 @@ anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer *cmd_buffer,
assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT);
assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
anv_cmd_compute_resolve_predicate(cmd_buffer, image,
aspect, 0, array_layer,
resolve_op, fast_clear_supported);
@ -1000,7 +1000,7 @@ init_fast_clear_color(struct anv_cmd_buffer *cmd_buffer,
} else {
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
sdi.Address = addr;
if (GEN_GEN >= 8 || GEN_IS_HASWELL) {
if (GEN_GEN >= 8 || GEN_VERSIONx10 == 75) {
/* Pre-SKL, the dword containing the clear values also contains
* other fields, so we need to initialize those fields to match the
* values that would be in a color attachment.
@ -1682,7 +1682,7 @@ genX(BeginCommandBuffer)(
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
}
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY) {
const VkCommandBufferInheritanceConditionalRenderingInfoEXT *conditional_rendering_info =
vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT);
@ -1801,7 +1801,7 @@ genX(CmdExecuteCommands)(
assert(secondary->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY);
assert(!anv_batch_has_error(&secondary->batch));
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
if (secondary->state.conditional_render_enabled) {
if (!primary->state.conditional_render_enabled) {
/* Secondary buffer is constructed as if it will be executed
@ -2144,7 +2144,7 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
if (bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT)
bits &= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES);
if (GEN_IS_HASWELL) {
if (GEN_VERSIONx10 == 75) {
/* Haswell needs addition work-arounds:
*
* From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
@ -2345,7 +2345,7 @@ cmd_buffer_alloc_push_constants(struct anv_cmd_buffer *cmd_buffer)
#if GEN_GEN >= 8
const unsigned push_constant_kb = 32;
#elif GEN_IS_HASWELL
#elif GEN_VERSIONx10 == 75
const unsigned push_constant_kb = cmd_buffer->device->info.gt == 3 ? 32 : 16;
#else
const unsigned push_constant_kb = 16;
@ -3053,7 +3053,7 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
c.MOCS = isl_mocs(&cmd_buffer->device->isl_dev, 0, false);
#endif
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
/* The Skylake PRM contains the following restriction:
*
* "The driver must ensure The following case does not occur
@ -3076,7 +3076,7 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
/* For Ivy Bridge, make sure we only set the first range (actual
* push constants)
*/
assert((GEN_GEN >= 8 || GEN_IS_HASWELL) || i == 0);
assert((GEN_GEN >= 8 || GEN_VERSIONx10 == 75) || i == 0);
c.ConstantBody.ReadLength[i + shift] = range->length;
c.ConstantBody.Buffer[i + shift] =
@ -3780,7 +3780,7 @@ void genX(CmdDrawIndirectByteCountEXT)(
uint32_t counterOffset,
uint32_t vertexStride)
{
#if GEN_IS_HASWELL || GEN_GEN >= 8
#if GEN_VERSIONx10 == 75 || GEN_GEN >= 8
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, counter_buffer, counterBuffer);
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
@ -3838,7 +3838,7 @@ void genX(CmdDrawIndirectByteCountEXT)(
}
update_dirty_vbs_for_gen8_vb_flush(cmd_buffer, SEQUENTIAL);
#endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
#endif /* GEN_VERSIONx10 == 75 || GEN_GEN >= 8 */
}
static void
@ -3855,7 +3855,7 @@ load_indirect_parameters(struct anv_cmd_buffer *cmd_buffer,
struct mi_value instance_count = mi_mem32(anv_address_add(addr, 4));
unsigned view_count = anv_subpass_view_count(cmd_buffer->state.subpass);
if (view_count > 1) {
#if GEN_IS_HASWELL || GEN_GEN >= 8
#if GEN_VERSIONx10 == 75 || GEN_GEN >= 8
instance_count = mi_imul_imm(&b, instance_count, view_count);
#else
anv_finishme("Multiview + indirect draw requires MI_MATH; "
@ -3987,7 +3987,7 @@ prepare_for_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
struct mi_value ret = mi_imm(0);
if (conditional_render_enabled) {
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
ret = mi_new_gpr(b);
mi_store(b, mi_value_ref(b, ret), mi_mem32(count_address));
#endif
@ -4032,7 +4032,7 @@ emit_draw_count_predicate(struct anv_cmd_buffer *cmd_buffer,
}
}
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
static void
emit_draw_count_predicate_with_conditional_render(
struct anv_cmd_buffer *cmd_buffer,
@ -4094,7 +4094,7 @@ void genX(CmdDrawIndirectCount)(
for (uint32_t i = 0; i < maxDrawCount; i++) {
struct anv_address draw = anv_address_add(buffer->address, offset);
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
if (cmd_state->conditional_render_enabled) {
emit_draw_count_predicate_with_conditional_render(
cmd_buffer, &b, i, mi_value_ref(&b, max));
@ -4165,7 +4165,7 @@ void genX(CmdDrawIndexedIndirectCount)(
for (uint32_t i = 0; i < maxDrawCount; i++) {
struct anv_address draw = anv_address_add(buffer->address, offset);
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
if (cmd_state->conditional_render_enabled) {
emit_draw_count_predicate_with_conditional_render(
cmd_buffer, &b, i, mi_value_ref(&b, max));
@ -4674,7 +4674,7 @@ void genX(CmdDispatchIndirect)(
mip.CompareOperation = COMPARE_FALSE;
}
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
if (cmd_buffer->state.conditional_render_enabled) {
/* predicate &= !(conditional_rendering_predicate == 0); */
mi_store(&b, mi_reg32(MI_PREDICATE_SRC0),
@ -6071,7 +6071,7 @@ void genX(CmdEndRenderPass2)(
void
genX(cmd_emit_conditional_render_predicate)(struct anv_cmd_buffer *cmd_buffer)
{
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
struct mi_builder b;
mi_builder_init(&b, &cmd_buffer->batch);
@ -6087,7 +6087,7 @@ genX(cmd_emit_conditional_render_predicate)(struct anv_cmd_buffer *cmd_buffer)
#endif
}
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
void genX(CmdBeginConditionalRenderingEXT)(
VkCommandBuffer commandBuffer,
const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin)

12
src/intel/vulkan/genX_pipeline.c
View File

@ -280,7 +280,7 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
entry_size, entries, start, deref_block_size,
&constrained);
#if GEN_GEN == 7 && !GEN_IS_HASWELL
#if GEN_GEN == 7 && GEN_VERSIONx10 != 75
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
*
* "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
@ -599,7 +599,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline,
sf.VertexSubPixelPrecisionSelect = _8Bit;
sf.AALineDistanceMode = true;
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
sf.LineStippleEnable = line_info && line_info->stippledLineEnable;
#endif
@ -2058,7 +2058,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
ps.DualSourceBlendEnable = dual_src_blend;
#endif
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
/* Haswell requires the sample mask to be set in this packet as well
* as in 3DSTATE_SAMPLE_MASK; the values should match.
*/
@ -2414,7 +2414,7 @@ emit_compute_state(struct anv_compute_pipeline *pipeline,
*/
vfe.PerThreadScratchSpace =
ffs(cs_bin->prog_data->total_scratch) - 11;
} else if (GEN_IS_HASWELL) {
} else if (GEN_VERSIONx10 == 75) {
/* Haswell's Per Thread Scratch Space is in the range [0, 10]
* where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
*/
@ -2447,11 +2447,11 @@ emit_compute_state(struct anv_compute_pipeline *pipeline,
.SharedLocalMemorySize =
encode_slm_size(GEN_GEN, cs_prog_data->base.total_shared),
#if !GEN_IS_HASWELL
#if GEN_VERSIONx10 != 75
.ConstantURBEntryReadOffset = 0,
#endif
.ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs,
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
.CrossThreadConstantDataReadLength =
cs_prog_data->push.cross_thread.regs,
#endif

2
src/intel/vulkan/genX_query.c
View File

@ -1294,7 +1294,7 @@ void genX(CmdWriteTimestamp)(
}
}
#if GEN_GEN > 7 || GEN_IS_HASWELL
#if GEN_GEN > 7 || GEN_VERSIONx10 == 75
#define MI_PREDICATE_SRC0 0x2400
#define MI_PREDICATE_SRC1 0x2408

10
src/intel/vulkan/genX_state.c
View File

@ -410,7 +410,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
l3sqc.ConvertIS_UC = !has_is;
l3sqc.ConvertC_UC = !has_c;
l3sqc.ConvertT_UC = !has_t;
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
l3sqc.L3SQGeneralPriorityCreditInitialization = SQGPCI_DEFAULT;
#else
l3sqc.L3SQGeneralPriorityCreditInitialization =
@ -423,7 +423,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
l3cr2.SLMEnable = cfg->n[INTEL_L3P_SLM];
l3cr2.URBLowBandwidth = urb_low_bw;
l3cr2.URBAllocation = cfg->n[INTEL_L3P_URB] - n0_urb;
#if !GEN_IS_HASWELL
#if !GEN_VERSIONx10 == 75
l3cr2.ALLAllocation = cfg->n[INTEL_L3P_ALL];
#endif
l3cr2.ROAllocation = cfg->n[INTEL_L3P_RO];
@ -439,7 +439,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
l3cr3.TLowBandwidth = 0;
}
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
if (device->physical->cmd_parser_version >= 4) {
/* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
* them disabled to avoid crashing the system hard.
@ -452,7 +452,7 @@ genX(emit_l3_config)(struct anv_batch *batch,
c3.L3AtomicDisable = !has_dc;
}
}
#endif /* GEN_IS_HASWELL */
#endif /* GEN_VERSIONx10 == 75 */
#endif /* GEN_GEN < 8 */
}
@ -656,7 +656,7 @@ VkResult genX(CreateSampler)(
vk_object_base_init(&device->vk, &sampler->base, VK_OBJECT_TYPE_SAMPLER);
sampler->n_planes = 1;
uint32_t border_color_stride = GEN_IS_HASWELL ? 512 : 64;
uint32_t border_color_stride = GEN_VERSIONx10 == 75 ? 512 : 64;
uint32_t border_color_offset;
ASSERTED bool has_custom_color = false;
if (pCreateInfo->borderColor <= VK_BORDER_COLOR_INT_OPAQUE_WHITE) {

4
src/mesa/drivers/dri/i965/genX_pipe_control.c
View File

@ -230,7 +230,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
flags |= PIPE_CONTROL_CS_STALL;
}
if (GEN_IS_HASWELL) {
if (GEN_VERSIONx10 == 75) {
/* From the PIPE_CONTROL page itself:
*
* "HSW - Programming Note: PIPECONTROL with RO Cache Invalidation:
@ -407,7 +407,7 @@ genX(emit_raw_pipe_control)(struct brw_context *brw, uint32_t flags,
* don't skip the ones with only read-cache-invalidate bits set. This
* may or may not be a problem...
*/
if (GEN_GEN == 7 && !GEN_IS_HASWELL) {
if (GEN_GEN == 7 && GEN_VERSIONx10 != 75) {
if (flags & PIPE_CONTROL_CS_STALL) {
/* If we're doing a CS stall, reset the counter and carry on. */
brw->pipe_controls_since_last_cs_stall = 0;

36
src/mesa/drivers/dri/i965/genX_state_upload.c
View File

@ -583,7 +583,7 @@ genX(emit_vertices)(struct brw_context *brw)
* vertex element may poke over the end of the buffer by 2 bytes.
*/
const unsigned padding =
(GEN_GEN <= 7 && !GEN_IS_HASWELL && !devinfo->is_baytrail) * 2;
(GEN_GEN <= 7 && GEN_VERSIONx10 != 75 && !devinfo->is_baytrail) * 2;
const unsigned end = buffer->offset + buffer->size + padding;
dw = genX(emit_vertex_buffer_state)(brw, dw, i, buffer->bo,
buffer->offset,
@ -864,7 +864,7 @@ genX(emit_index_buffer)(struct brw_context *brw)
vf_invalidate_for_ib_48bit_transition(brw);
brw_batch_emit(brw, GENX(3DSTATE_INDEX_BUFFER), ib) {
#if GEN_GEN < 8 && !GEN_IS_HASWELL
#if GEN_GEN < 8 && GEN_VERSIONx10 != 75
assert(brw->ib.enable_cut_index == brw->prim_restart.enable_cut_index);
ib.CutIndexEnable = brw->ib.enable_cut_index;
#endif
@ -897,7 +897,7 @@ static const struct brw_tracked_state genX(index_buffer) = {
.emit = genX(emit_index_buffer),
};
#if GEN_IS_HASWELL || GEN_GEN >= 8
#if GEN_VERSIONx10 == 75 || GEN_GEN >= 8
static void
genX(upload_cut_index)(struct brw_context *brw)
{
@ -1628,7 +1628,7 @@ genX(upload_sf)(struct brw_context *brw)
sf.CullMode = CULLMODE_NONE;
}
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
sf.LineStippleEnable = ctx->Line.StippleFlag;
#endif
@ -2032,7 +2032,7 @@ genX(upload_wm)(struct brw_context *brw)
* BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | _NEW_BUFFERS |
* _NEW_COLOR
*/
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
if (!(brw_color_buffer_write_enabled(brw) || writes_depth) &&
wm_prog_data->has_side_effects)
wm.PSUAVonly = ON;
@ -2579,7 +2579,7 @@ genX(upload_gs_state)(struct brw_context *brw)
}
#endif
#if GEN_GEN == 7 && !GEN_IS_HASWELL
#if GEN_GEN == 7 && GEN_VERSIONx10 != 75
/**
* From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
* Geometry > Geometry Shader > State:
@ -3092,7 +3092,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw)
&brw->wm.base,
};
if (GEN_GEN == 7 && !GEN_IS_HASWELL && !devinfo->is_baytrail &&
if (GEN_GEN == 7 && GEN_VERSIONx10 != 75 && !devinfo->is_baytrail &&
stage_states[MESA_SHADER_VERTEX]->push_constants_dirty)
gen7_emit_vs_workaround_flush(brw);
@ -3106,7 +3106,7 @@ genX(upload_push_constant_packets)(struct brw_context *brw)
brw_batch_emit(brw, GENX(3DSTATE_CONSTANT_VS), pkt) {
pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
if (stage_state->prog_data) {
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
/* The Skylake PRM contains the following restriction:
*
* "The driver must ensure The following case does not occur
@ -3431,7 +3431,7 @@ UNUSED static const struct brw_tracked_state genX(color_calc_state) = {
/* ---------------------------------------------------------------------- */
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
static void
genX(upload_color_calc_and_blend_state)(struct brw_context *brw)
{
@ -3886,7 +3886,7 @@ genX(upload_ps)(struct brw_context *brw)
*/
/* _NEW_BUFFERS, _NEW_MULTISAMPLE */
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
ps.SampleMask = genX(determine_sample_mask(brw));
#endif
@ -4305,7 +4305,7 @@ genX(upload_cs_state)(struct brw_context *brw)
* where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
*/
per_thread_scratch_value = ffs(stage_state->per_thread_scratch) - 11;
} else if (GEN_IS_HASWELL) {
} else if (GEN_VERSIONx10 == 75) {
/* Haswell's Per Thread Scratch Space is in the range [0, 10]
* where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
*/
@ -4394,7 +4394,7 @@ genX(upload_cs_state)(struct brw_context *brw)
.SharedLocalMemorySize = encode_slm_size(GEN_GEN,
prog_data->total_shared),
.BarrierEnable = cs_prog_data->uses_barrier,
#if GEN_GEN >= 8 || GEN_IS_HASWELL
#if GEN_GEN >= 8 || GEN_VERSIONx10 == 75
.CrossThreadConstantDataReadLength =
cs_prog_data->push.cross_thread.regs,
#endif
@ -4925,7 +4925,7 @@ genX(emit_sampler_state_pointers_xs)(UNUSED struct brw_context *brw,
};
/* Ivybridge requires a workaround flush before VS packets. */
if (GEN_GEN == 7 && !GEN_IS_HASWELL &&
if (GEN_GEN == 7 && GEN_VERSIONx10 != 75 &&
stage_state->stage == MESA_SHADER_VERTEX) {
gen7_emit_vs_workaround_flush(brw);
}
@ -5013,7 +5013,7 @@ genX(upload_default_color)(struct brw_context *brw,
int alignment = 32;
if (GEN_GEN >= 8) {
alignment = 64;
} else if (GEN_IS_HASWELL && (is_integer_format || is_stencil_sampling)) {
} else if (GEN_VERSIONx10 == 75 && (is_integer_format || is_stencil_sampling)) {
alignment = 512;
}
@ -5051,7 +5051,7 @@ genX(upload_default_color)(struct brw_context *brw,
* memcpy the values.
*/
BORDER_COLOR_ATTR(ASSIGN, 32bit, color.ui);
#elif GEN_IS_HASWELL
#elif GEN_VERSIONx10 == 75
if (is_integer_format || is_stencil_sampling) {
bool stencil = format == MESA_FORMAT_S_UINT8 || is_stencil_sampling;
const int bits_per_channel =
@ -5276,7 +5276,7 @@ genX(update_sampler_state)(struct brw_context *brw,
* integer formats. Fall back to CLAMP for now.
*/
if ((tex_cube_map_seamless || sampler->Attrib.CubeMapSeamless) &&
!(GEN_GEN == 7 && !GEN_IS_HASWELL && texObj->_IsIntegerFormat)) {
!(GEN_GEN == 7 && GEN_VERSIONx10 != 75 && texObj->_IsIntegerFormat)) {
wrap_s = TCM_CUBE;
wrap_t = TCM_CUBE;
wrap_r = TCM_CUBE;
@ -5719,7 +5719,7 @@ genX(init_atoms)(struct brw_context *brw)
&gen7_l3_state,
&gen7_push_constant_space,
&gen7_urb,
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
&genX(cc_and_blend_state),
#else
&genX(blend_state), /* must do before cc unit */
@ -5798,7 +5798,7 @@ genX(init_atoms)(struct brw_context *brw)
&genX(index_buffer),
&genX(vertices),
#if GEN_IS_HASWELL
#if GEN_VERSIONx10 == 75
&genX(cut_index),
#endif
};