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anv,iris: L3ALLOC register replaces L3CNTLREG for gen12 

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jordan Justen 2017-12-12 20:24:57 -08:00
parent 414cae0fd6
commit 9790cfcefa
No known key found for this signature in database
GPG Key ID: 37F99F68CAF992EB
3 changed files with 29 additions and 9 deletions
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15
src/gallium/drivers/iris/iris_state.c
View File

@ -607,8 +607,19 @@ iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg,
bool has_slm, bool wants_dc_cache)
{
uint32_t reg_val;
iris_pack_state(GENX(L3CNTLREG), &reg_val, reg) {
#if GEN_GEN >= 12
#define L3_ALLOCATION_REG GENX(L3ALLOC)
#define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
#else
#define L3_ALLOCATION_REG GENX(L3CNTLREG)
#define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
#endif
iris_pack_state(L3_ALLOCATION_REG, &reg_val, reg) {
#if GEN_GEN < 12
reg.SLMEnable = has_slm;
#endif
#if GEN_GEN == 11
/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
* in L3CNTLREG register. The default setting of the bit is not the
@ -622,7 +633,7 @@ iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg,
reg.DCAllocation = cfg->n[GEN_L3P_DC];
reg.AllAllocation = cfg->n[GEN_L3P_ALL];
}
iris_emit_lri(batch, L3CNTLREG, reg_val);
_iris_emit_lri(batch, L3_ALLOCATION_REG_num, reg_val);
}
static void

7
src/intel/genxml/gen12.xml
View File

@ -6991,11 +6991,10 @@
<field name="TSG1 Done" start="24" end="24" type="bool"/>
</register>
<register name="L3CNTLREG" length="1" num="0x7034">
<field name="SLM Enable" start="0" end="0" type="uint"/>
<register name="L3ALLOC" length="1" num="0xB134">
<field name="Allocation Error" start="0" end="0" type="uint"/>
<field name="URB Allocation" start="1" end="7" type="uint"/>
<field name="Error Detection Behavior Control" start="9" end="9" type="bool"/>
<field name="Use Full Ways" start="10" end="10" type="bool"/>
<field name="L3 Full Way Allocation Enable" start="9" end="9" type="bool"/>
<field name="RO Allocation" start="11" end="17" type="uint"/>
<field name="DC Allocation" start="18" end="24" type="uint"/>
<field name="All Allocation" start="25" end="31" type="uint"/>

16
src/intel/vulkan/genX_cmd_buffer.c
View File

@ -1627,7 +1627,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
gen_dump_l3_config(cfg, stderr);
}
const bool has_slm = cfg->n[GEN_L3P_SLM];
UNUSED const bool has_slm = cfg->n[GEN_L3P_SLM];
/* According to the hardware docs, the L3 partitioning can only be changed
* while the pipeline is completely drained and the caches are flushed,
@ -1674,9 +1674,19 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
assert(!cfg->n[GEN_L3P_IS] && !cfg->n[GEN_L3P_C] && !cfg->n[GEN_L3P_T]);
#if GEN_GEN >= 12
#define L3_ALLOCATION_REG GENX(L3ALLOC)
#define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
#else
#define L3_ALLOCATION_REG GENX(L3CNTLREG)
#define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
#endif
uint32_t l3cr;
anv_pack_struct(&l3cr, GENX(L3CNTLREG),
anv_pack_struct(&l3cr, L3_ALLOCATION_REG,
#if GEN_GEN < 12
.SLMEnable = has_slm,
#endif
#if GEN_GEN == 11
/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
* in L3CNTLREG register. The default setting of the bit is not the
@ -1691,7 +1701,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer,
.AllAllocation = cfg->n[GEN_L3P_ALL]);
/* Set up the L3 partitioning. */
emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG_num), l3cr);
emit_lri(&cmd_buffer->batch, L3_ALLOCATION_REG_num, l3cr);
#else