v3d: Add support for using the TFU to do some blits.
This will be useful in particular for blits from raster to UIF for X11.
This commit is contained in:
Eric Anholt
parent
e5b4d1f55f
commit
976ea90bdc
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@ -330,6 +330,8 @@ v3d_stencil_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
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#define V3D_TFU_ICFG_NUMMM_SHIFT 5
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#define V3D_TFU_ICFG_TTYPE_SHIFT 9
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#define V3D_TFU_ICFG_OPAD_SHIFT 22
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#define V3D_TFU_ICFG_FORMAT_SHIFT 18
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#define V3D_TFU_ICFG_FORMAT_RASTER 0
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#define V3D_TFU_ICFG_FORMAT_SAND_128 1
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@ -340,6 +342,121 @@ v3d_stencil_blit(struct pipe_context *ctx, const struct pipe_blit_info *info)
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#define V3D_TFU_ICFG_FORMAT_UIF_NO_XOR 14
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#define V3D_TFU_ICFG_FORMAT_UIF_XOR 15
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static bool
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v3d_tfu(struct pipe_context *pctx,
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struct pipe_resource *pdst,
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struct pipe_resource *psrc,
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unsigned int src_level,
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unsigned int base_level,
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unsigned int last_level,
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unsigned int src_layer,
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unsigned int dst_layer)
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{
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struct v3d_context *v3d = v3d_context(pctx);
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struct v3d_screen *screen = v3d->screen;
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struct v3d_resource *src = v3d_resource(psrc);
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struct v3d_resource *dst = v3d_resource(pdst);
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struct v3d_resource_slice *src_base_slice = &src->slices[src_level];
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struct v3d_resource_slice *dst_base_slice = &dst->slices[base_level];
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int msaa_scale = pdst->nr_samples > 1 ? 2 : 1;
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int width = u_minify(pdst->width0, base_level) * msaa_scale;
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int height = u_minify(pdst->height0, base_level) * msaa_scale;
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if (psrc->format != pdst->format)
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return false;
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if (psrc->nr_samples != pdst->nr_samples)
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return false;
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uint32_t tex_format = v3d_get_tex_format(&screen->devinfo,
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pdst->format);
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if (!v3d_tfu_supports_tex_format(&screen->devinfo, tex_format))
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return false;
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if (pdst->target != PIPE_TEXTURE_2D || psrc->target != PIPE_TEXTURE_2D)
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return false;
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/* Can't write to raster. */
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if (dst_base_slice->tiling == VC5_TILING_RASTER)
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return false;
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v3d_flush_jobs_writing_resource(v3d, psrc);
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v3d_flush_jobs_reading_resource(v3d, pdst);
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struct drm_v3d_submit_tfu tfu = {
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.ios = (height << 16) | width,
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.bo_handles = {
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src->bo->handle,
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src != dst ? dst->bo->handle : 0
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},
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.in_sync = v3d->out_sync,
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.out_sync = v3d->out_sync,
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};
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uint32_t src_offset = (src->bo->offset +
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v3d_layer_offset(psrc, src_level, src_layer));
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tfu.iia |= src_offset;
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if (src_base_slice->tiling == VC5_TILING_RASTER) {
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tfu.icfg |= (V3D_TFU_ICFG_FORMAT_RASTER <<
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V3D_TFU_ICFG_FORMAT_SHIFT);
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} else {
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tfu.icfg |= ((V3D_TFU_ICFG_FORMAT_LINEARTILE +
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(src_base_slice->tiling - VC5_TILING_LINEARTILE)) <<
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V3D_TFU_ICFG_FORMAT_SHIFT);
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}
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uint32_t dst_offset = (dst->bo->offset +
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v3d_layer_offset(pdst, src_level, dst_layer));
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tfu.ioa |= dst_offset;
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if (last_level != base_level)
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tfu.ioa |= V3D_TFU_IOA_DIMTW;
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tfu.ioa |= ((V3D_TFU_IOA_FORMAT_LINEARTILE +
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(dst_base_slice->tiling - VC5_TILING_LINEARTILE)) <<
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V3D_TFU_IOA_FORMAT_SHIFT);
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tfu.icfg |= tex_format << V3D_TFU_ICFG_TTYPE_SHIFT;
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tfu.icfg |= (last_level - base_level) << V3D_TFU_ICFG_NUMMM_SHIFT;
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switch (src_base_slice->tiling) {
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case VC5_TILING_UIF_NO_XOR:
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case VC5_TILING_UIF_XOR:
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tfu.iis |= (src_base_slice->padded_height /
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(2 * v3d_utile_height(src->cpp)));
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break;
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case VC5_TILING_RASTER:
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tfu.iis |= src_base_slice->stride / src->cpp;
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break;
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case VC5_TILING_LINEARTILE:
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case VC5_TILING_UBLINEAR_1_COLUMN:
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case VC5_TILING_UBLINEAR_2_COLUMN:
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break;
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}
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/* If we're writing level 0 (!IOA_DIMTW), then we need to supply the
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* OPAD field for the destination (how many extra UIF blocks beyond
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* those necessary to cover the height). When filling mipmaps, the
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* miplevel 1+ tiling state is inferred.
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*/
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if (dst_base_slice->tiling == VC5_TILING_UIF_NO_XOR ||
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dst_base_slice->tiling == VC5_TILING_UIF_XOR) {
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int uif_block_h = 2 * v3d_utile_height(dst->cpp);
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int implicit_padded_height = align(height, uif_block_h);
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tfu.icfg |= (((dst_base_slice->padded_height -
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implicit_padded_height) / uif_block_h) <<
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V3D_TFU_ICFG_OPAD_SHIFT);
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}
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int ret = v3d_ioctl(screen->fd, DRM_IOCTL_V3D_SUBMIT_TFU, &tfu);
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if (ret != 0) {
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fprintf(stderr, "Failed to submit TFU job: %d\n", ret);
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return false;
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}
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dst->writes++;
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return true;
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}
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boolean
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v3d_generate_mipmap(struct pipe_context *pctx,
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struct pipe_resource *prsc,
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@ -349,78 +466,49 @@ v3d_generate_mipmap(struct pipe_context *pctx,
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unsigned int first_layer,
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unsigned int last_layer)
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{
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struct v3d_context *v3d = v3d_context(pctx);
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struct v3d_screen *screen = v3d->screen;
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struct v3d_resource *rsc = v3d_resource(prsc);
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struct v3d_resource_slice *base_slice = &rsc->slices[base_level];
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int width = u_minify(prsc->width0, base_level);
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int height = u_minify(prsc->height0, base_level);
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uint32_t tex_format = v3d_get_tex_format(&screen->devinfo,
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prsc->format);
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if (!v3d_tfu_supports_tex_format(&screen->devinfo, tex_format))
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if (format != prsc->format)
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return false;
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if (prsc->target != PIPE_TEXTURE_2D)
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return false;
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/* Since we don't support array or 3D textures, there should be only
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* one layer.
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/* We could maybe support looping over layers for array textures, but
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* we definitely don't support 3D.
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*/
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int layer = first_layer;
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assert(first_layer == last_layer);
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/* Can't write to raster. */
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if (base_slice->tiling == VC5_TILING_RASTER)
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if (first_layer != last_layer)
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return false;
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v3d_flush_jobs_reading_resource(v3d, prsc);
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return v3d_tfu(pctx,
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prsc, prsc,
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base_level,
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base_level, last_level,
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first_layer, first_layer);
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}
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struct drm_v3d_submit_tfu tfu = {
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.ios = (height << 16) | width,
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.bo_handles = { rsc->bo->handle },
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.in_sync = v3d->out_sync,
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.out_sync = v3d->out_sync,
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};
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uint32_t offset = (rsc->bo->offset +
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v3d_layer_offset(prsc, base_level, layer));
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tfu.iia |= offset;
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tfu.icfg |= ((V3D_TFU_ICFG_FORMAT_LINEARTILE +
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(base_slice->tiling - VC5_TILING_LINEARTILE)) <<
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V3D_TFU_ICFG_FORMAT_SHIFT);
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static bool
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v3d_tfu_blit(struct pipe_context *pctx, const struct pipe_blit_info *info)
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{
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int dst_width = u_minify(info->dst.resource->width0, info->dst.level);
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int dst_height = u_minify(info->dst.resource->height0, info->dst.level);
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tfu.ioa |= offset;
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tfu.ioa |= V3D_TFU_IOA_DIMTW;
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tfu.ioa |= ((V3D_TFU_IOA_FORMAT_LINEARTILE +
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(base_slice->tiling - VC5_TILING_LINEARTILE)) <<
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V3D_TFU_IOA_FORMAT_SHIFT);
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if ((info->mask & PIPE_MASK_RGBA) == 0)
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return false;
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tfu.icfg |= tex_format << V3D_TFU_ICFG_TTYPE_SHIFT;
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tfu.icfg |= (last_level - base_level) << V3D_TFU_ICFG_NUMMM_SHIFT;
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switch (base_slice->tiling) {
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case VC5_TILING_UIF_NO_XOR:
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case VC5_TILING_UIF_XOR:
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tfu.iis |= (base_slice->padded_height /
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(2 * v3d_utile_height(rsc->cpp)));
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break;
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case VC5_TILING_RASTER:
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tfu.iis |= base_slice->stride / rsc->cpp;
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break;
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case VC5_TILING_LINEARTILE:
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case VC5_TILING_UBLINEAR_1_COLUMN:
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case VC5_TILING_UBLINEAR_2_COLUMN:
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break;
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}
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int ret = v3d_ioctl(screen->fd, DRM_IOCTL_V3D_SUBMIT_TFU, &tfu);
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if (ret != 0) {
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fprintf(stderr, "Failed to submit TFU job: %d\n", ret);
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if (info->dst.box.x != 0 ||
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info->dst.box.y != 0 ||
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info->dst.box.width != dst_width ||
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info->dst.box.height != dst_height ||
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info->src.box.x != 0 ||
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info->src.box.y != 0 ||
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info->src.box.width != info->dst.box.width ||
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info->src.box.height != info->dst.box.height) {
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return false;
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}
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rsc->writes++;
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if (info->dst.format != info->src.format)
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return false;
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return true;
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return v3d_tfu(pctx, info->dst.resource, info->src.resource,
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info->src.level,
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info->dst.level, info->dst.level,
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info->src.box.z, info->dst.box.z);
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}
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/* Optimal hardware path for blitting pixels.
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@ -436,10 +524,9 @@ v3d_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
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info.mask &= ~PIPE_MASK_S;
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}
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#if 0
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if (v3d_tile_blit(pctx, blit_info))
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return;
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#endif
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if (v3d_tfu_blit(pctx, blit_info))
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info.mask &= ~PIPE_MASK_RGBA;
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v3d_render_blit(pctx, &info);
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if (info.mask)
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v3d_render_blit(pctx, &info);
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}
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