intel/fs/xehp+: Emit scheduling fence for all NIR barriers on platforms with LSC.
Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15743>
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@ -4623,7 +4623,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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assert(fence_regs_count <= ARRAY_SIZE(fence_regs));
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assert(fence_regs_count <= ARRAY_SIZE(fence_regs));
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/* There are three cases where we want to insert a stall:
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/* There are four cases where we want to insert a stall:
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*
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*
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* 1. If we're a nir_intrinsic_end_invocation_interlock. This is
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* 1. If we're a nir_intrinsic_end_invocation_interlock. This is
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* required to ensure that the shader EOT doesn't happen until
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* required to ensure that the shader EOT doesn't happen until
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@ -4637,9 +4637,11 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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* 3. If we have no fences. In this case, we need at least a
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* 3. If we have no fences. In this case, we need at least a
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* scheduling barrier to keep the compiler from moving things
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* scheduling barrier to keep the compiler from moving things
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* around in an invalid way.
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* around in an invalid way.
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*
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* 4. On platforms with LSC.
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*/
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*/
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if (instr->intrinsic == nir_intrinsic_end_invocation_interlock ||
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if (instr->intrinsic == nir_intrinsic_end_invocation_interlock ||
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fence_regs_count != 1) {
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fence_regs_count != 1 || devinfo->has_lsc) {
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ubld.exec_all().group(1, 0).emit(
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ubld.exec_all().group(1, 0).emit(
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FS_OPCODE_SCHEDULING_FENCE, ubld.null_reg_ud(),
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FS_OPCODE_SCHEDULING_FENCE, ubld.null_reg_ud(),
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fence_regs, fence_regs_count);
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fence_regs, fence_regs_count);
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