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intel/fs/xehp+: Emit scheduling fence for all NIR barriers on platforms with LSC. 

Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15743>
This commit is contained in:
Francisco Jerez 2022-04-27 09:20:21 +03:00 committed by Tapani Pälli
parent 47773a5d7c
commit 96e7e92f0d
1 changed files with 4 additions and 2 deletions
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6
src/intel/compiler/brw_fs_nir.cpp
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@ -4623,7 +4623,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
assert(fence_regs_count <= ARRAY_SIZE(fence_regs));
/* There are three cases where we want to insert a stall:
/* There are four cases where we want to insert a stall:
*
* 1. If we're a nir_intrinsic_end_invocation_interlock. This is
* required to ensure that the shader EOT doesn't happen until
@ -4637,9 +4637,11 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
* 3. If we have no fences. In this case, we need at least a
* scheduling barrier to keep the compiler from moving things
* around in an invalid way.
*
* 4. On platforms with LSC.
*/
if (instr->intrinsic == nir_intrinsic_end_invocation_interlock ||
fence_regs_count != 1) {
fence_regs_count != 1 || devinfo->has_lsc) {
ubld.exec_all().group(1, 0).emit(
FS_OPCODE_SCHEDULING_FENCE, ubld.null_reg_ud(),
fence_regs, fence_regs_count);