i965/compiler: handle conversion to smaller type in the lowering pass for that
The lowering pass was specialized to act on 64-bit to 32-bit conversions only, but the implementation is valid for other cases. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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5361a87ee7
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@ -54,7 +54,7 @@ fs_visitor::lower_conversions()
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bool saturate = inst->saturate;
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if (supports_type_conversion(inst)) {
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if (get_exec_type_size(inst) == 8 && type_sz(inst->dst.type) < 8) {
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if (type_sz(inst->dst.type) < get_exec_type_size(inst)) {
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/* From the Broadwell PRM, 3D Media GPGPU, "Double Precision Float to
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* Single Precision Float":
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*
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@ -64,6 +64,9 @@ fs_visitor::lower_conversions()
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* So we need to allocate a temporary that's two registers, and then do
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* a strided MOV to get the lower DWord of every Qword that has the
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* result.
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*
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* This restriction applies, in general, whenever we convert to
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* a type with a smaller bit-size.
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*/
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fs_reg temp = ibld.vgrf(get_exec_type(inst));
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fs_reg strided_temp = subscript(temp, dst.type, 0);
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@ -755,19 +755,9 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
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*/
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case nir_op_f2f16_undef:
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case nir_op_i2i16:
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case nir_op_u2u16: {
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/* TODO: Fixing aligment rules for conversions from 32-bits to
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* 16-bit types should be moved to lower_conversions
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*/
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fs_reg tmp = bld.vgrf(op[0].type, 1);
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tmp = subscript(tmp, result.type, 0);
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inst = bld.MOV(tmp, op[0]);
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inst->saturate = instr->dest.saturate;
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inst = bld.MOV(result, tmp);
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inst = bld.MOV(result, op[0]);
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inst->saturate = instr->dest.saturate;
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break;
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}
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case nir_op_f2f64:
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case nir_op_f2i64:
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@ -805,6 +795,8 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
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case nir_op_f2u32:
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case nir_op_i2i32:
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case nir_op_u2u32:
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case nir_op_i2i16:
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case nir_op_u2u16:
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inst = bld.MOV(result, op[0]);
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inst->saturate = instr->dest.saturate;
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break;
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