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gallium/radeon/winsyses: expose per-IB used_vram and used_gart to drivers 

The following patches will use this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-07-29 21:39:00 +02:00
parent 1c8f17599e
commit 9646ae7799
5 changed files with 24 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/gallium/drivers/radeon/radeon_winsys.h
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@ -236,6 +236,11 @@ struct radeon_winsys_cs {
unsigned num_prev; /* Number of previous chunks. */
unsigned max_prev; /* Space in array pointed to by prev. */
unsigned prev_dw; /* Total number of dwords in previous chunks. */
/* Memory usage of the buffer list. These are always 0 for CE and preamble
* IBs. */
uint64_t used_vram;
uint64_t used_gart;
};
struct radeon_info {

17
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
View File

@ -343,9 +343,9 @@ static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
priority, &added_domains);
if (added_domains & RADEON_DOMAIN_VRAM)
cs->csc->used_vram += bo->base.size;
cs->main.base.used_vram += bo->base.size;
else if (added_domains & RADEON_DOMAIN_GTT)
cs->csc->used_gart += bo->base.size;
cs->main.base.used_gart += bo->base.size;
return index;
}
@ -571,8 +571,6 @@ static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *cs)
}
cs->num_buffers = 0;
cs->used_gart = 0;
cs->used_vram = 0;
amdgpu_fence_reference(&cs->fence, NULL);
for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
@ -790,8 +788,8 @@ static bool amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs,
struct amdgpu_cs *cs = amdgpu_cs(rcs);
struct amdgpu_winsys *ws = cs->ctx->ws;
vram += cs->csc->used_vram;
gtt += cs->csc->used_gart;
vram += cs->main.base.used_vram;
gtt += cs->main.base.used_gart;
/* Anything that goes above the VRAM size should go to GTT. */
if (vram > ws->info.vram_size)
@ -803,9 +801,7 @@ static bool amdgpu_cs_memory_below_limit(struct radeon_winsys_cs *rcs,
static uint64_t amdgpu_cs_query_memory_usage(struct radeon_winsys_cs *rcs)
{
struct amdgpu_cs_context *cs = amdgpu_cs(rcs)->csc;
return cs->used_vram + cs->used_gart;
return rcs->used_vram + rcs->used_gart;
}
static unsigned amdgpu_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
@ -1073,6 +1069,9 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
if (cs->const_preamble_ib.ib_mapped)
amdgpu_get_new_ib(&ws->base, cs, IB_CONST_PREAMBLE);
cs->main.base.used_gart = 0;
cs->main.base.used_vram = 0;
ws->num_cs_flushes++;
return error_code;
}

2
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
View File

@ -82,8 +82,6 @@ struct amdgpu_cs_context {
int buffer_indices_hashlist[4096];
uint64_t used_vram;
uint64_t used_gart;
unsigned max_dependencies;

22
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
View File

@ -147,8 +147,6 @@ static void radeon_cs_context_cleanup(struct radeon_cs_context *csc)
csc->validated_crelocs = 0;
csc->chunks[0].length_dw = 0;
csc->chunks[1].length_dw = 0;
csc->used_gart = 0;
csc->used_vram = 0;
for (i = 0; i < ARRAY_SIZE(csc->reloc_indices_hashlist); i++) {
csc->reloc_indices_hashlist[i] = -1;
@ -332,9 +330,9 @@ static unsigned radeon_drm_cs_add_buffer(struct radeon_winsys_cs *rcs,
&added_domains);
if (added_domains & RADEON_DOMAIN_VRAM)
cs->csc->used_vram += bo->base.size;
cs->base.used_vram += bo->base.size;
else if (added_domains & RADEON_DOMAIN_GTT)
cs->csc->used_gart += bo->base.size;
cs->base.used_gart += bo->base.size;
return index;
}
@ -351,8 +349,8 @@ static bool radeon_drm_cs_validate(struct radeon_winsys_cs *rcs)
{
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
bool status =
cs->csc->used_gart < cs->ws->info.gart_size * 0.8 &&
cs->csc->used_vram < cs->ws->info.vram_size * 0.8;
cs->base.used_gart < cs->ws->info.gart_size * 0.8 &&
cs->base.used_vram < cs->ws->info.vram_size * 0.8;
if (status) {
cs->csc->validated_crelocs = cs->csc->crelocs;
@ -373,6 +371,8 @@ static bool radeon_drm_cs_validate(struct radeon_winsys_cs *rcs)
cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC, NULL);
} else {
radeon_cs_context_cleanup(cs->csc);
cs->base.used_vram = 0;
cs->base.used_gart = 0;
assert(cs->base.current.cdw == 0);
if (cs->base.current.cdw != 0) {
@ -393,8 +393,8 @@ static bool radeon_drm_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint6
{
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
vram += cs->csc->used_vram;
gtt += cs->csc->used_gart;
vram += cs->base.used_vram;
gtt += cs->base.used_gart;
/* Anything that goes above the VRAM size should go to GTT. */
if (vram > cs->ws->info.vram_size)
@ -406,9 +406,7 @@ static bool radeon_drm_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint6
static uint64_t radeon_drm_cs_query_memory_usage(struct radeon_winsys_cs *rcs)
{
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
return cs->csc->used_vram + cs->csc->used_gart;
return rcs->used_vram + rcs->used_gart;
}
static unsigned radeon_drm_cs_get_buffer_list(struct radeon_winsys_cs *rcs,
@ -597,6 +595,8 @@ static int radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
/* Prepare a new CS. */
cs->base.current.buf = cs->csc->buf;
cs->base.current.cdw = 0;
cs->base.used_vram = 0;
cs->base.used_gart = 0;
cs->ws->num_cs_flushes++;
return 0;

3
src/gallium/winsys/radeon/drm/radeon_drm_cs.h
View File

@ -52,9 +52,6 @@ struct radeon_cs_context {
uint64_t *priority_usage;
int reloc_indices_hashlist[4096];
uint64_t used_vram;
uint64_t used_gart;
};
struct radeon_drm_cs {