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i965g: make the winsys responsible for all buffer->offset handling 

The winsys now inserts the presumed offset into referring buffers from
inside of bo_emit_reloc().  Remove the many locally coded places where
this was happening in the driver and eliminate the worry of getting it
wrong.

No longer need to expose offset values to the driver at all, so no need
to worry about what to do in the driver when they change.  Just use
zero values wherever we had offsets previously -- the relocations will
fix it all up for us.
This commit is contained in:
Keith Whitwell 2009-11-05 20:34:27 +00:00
parent 658da189b6
commit 963728665a
12 changed files with 29 additions and 30 deletions
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11
src/gallium/drivers/i965/brw_batchbuffer.c
View File

@ -115,7 +115,7 @@ _brw_batchbuffer_flush(struct brw_batchbuffer *batch,
file, line, used);
if (ALWAYS_EMIT_MI_FLUSH) {
*(GLuint *) (batch->ptr) = ((MI_FLUSH << 16) | BRW_FLUSH_STATE_CACHE);
*(GLuint *) (batch->ptr) = MI_FLUSH | BRW_FLUSH_STATE_CACHE;
batch->ptr += 4;
used = batch->ptr - batch->map;
}
@ -192,12 +192,11 @@ brw_batchbuffer_emit_reloc(struct brw_batchbuffer *batch,
if (ret != 0)
return ret;
/*
* Using the old buffer offset, write in what the right data would be, in case
* the buffer doesn't move and we can short-circuit the relocation processing
* in the kernel
/* bo_emit_reloc was resposible for writing a zero into the
* batchbuffer if necessary. Just need to update our pointer.
*/
brw_batchbuffer_emit_dword (batch, buffer->offset[0] + delta);
batch->ptr += 4;
return 0;
}

2
src/gallium/drivers/i965/brw_cc.c
View File

@ -142,7 +142,7 @@ cc_unit_create_from_key(struct brw_context *brw,
cc.cc3 = key->cc3;
/* CACHE_NEW_CC_VP */
cc.cc4.cc_viewport_state_offset = *(brw->cc.vp_bo->offset) >> 5; /* reloc */
cc.cc4.cc_viewport_state_offset = 0;
cc.cc5 = key->cc5;
cc.cc6 = key->cc6;

2
src/gallium/drivers/i965/brw_clip_state.c
View File

@ -84,7 +84,7 @@ clip_unit_create_from_key(struct brw_context *brw,
clip.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
/* reloc */
clip.thread0.kernel_start_pointer = *(brw->clip.prog_bo->offset) >> 6;
clip.thread0.kernel_start_pointer = 0;
clip.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
clip.thread1.single_program_flow = 1;

4
src/gallium/drivers/i965/brw_gs_state.c
View File

@ -80,8 +80,8 @@ gs_unit_create_from_key(struct brw_context *brw,
memset(&gs, 0, sizeof(gs));
gs.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
if (key->prog_active) /* reloc */
gs.thread0.kernel_start_pointer = brw->gs.prog_bo->offset[0] >> 6;
/* reloc */
gs.thread0.kernel_start_pointer = 0;
gs.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
gs.thread1.single_program_flow = 1;

8
src/gallium/drivers/i965/brw_screen_texture.c
View File

@ -211,8 +211,10 @@ static struct pipe_texture *brw_texture_create( struct pipe_screen *screen,
/* && bscreen->use_texture_tiling */
/* && bscreen->kernel_exec_fencing */)
{
if (bscreen->chipset.is_965 &&
pf_is_depth_or_stencil(templ->format))
if (1)
tex->tiling = BRW_TILING_NONE;
else if (bscreen->chipset.is_965 &&
pf_is_depth_or_stencil(templ->format))
tex->tiling = BRW_TILING_Y;
else
tex->tiling = BRW_TILING_X;
@ -256,7 +258,7 @@ static struct pipe_texture *brw_texture_create( struct pipe_screen *screen,
/* XXX: what happens when tex->bo->offset changes???
*/
tex->ss.ss1.base_addr = tex->bo->offset[0]; /* reloc */
tex->ss.ss1.base_addr = 0; /* reloc */
tex->ss.ss2.mip_count = tex->base.last_level;
tex->ss.ss2.width = tex->base.width[0] - 1;
tex->ss.ss2.height = tex->base.height[0] - 1;

6
src/gallium/drivers/i965/brw_sf_state.c
View File

@ -142,7 +142,8 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
memset(&sf, 0, sizeof(sf));
sf.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
sf.thread0.kernel_start_pointer = brw->sf.prog_bo->offset[0] >> 6; /* reloc */
/* reloc */
sf.thread0.kernel_start_pointer = 0;
sf.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
@ -175,7 +176,8 @@ sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
sf.thread4.stats_enable = 1;
/* CACHE_NEW_SF_VP */
sf.sf5.sf_viewport_state_offset = brw->sf.vp_bo->offset[0] >> 5; /* reloc */
/* reloc */
sf.sf5.sf_viewport_state_offset = 0;
sf.sf5.viewport_transform = 1;

2
src/gallium/drivers/i965/brw_vs_state.c
View File

@ -89,7 +89,7 @@ vs_unit_create_from_key(struct brw_context *brw,
memset(&vs, 0, sizeof(vs));
vs.thread0.kernel_start_pointer = brw->vs.prog_bo->offset[0] >> 6; /* reloc */
vs.thread0.kernel_start_pointer = 0; /* reloc */
vs.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
vs.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
/* Choosing multiple program flow means that we may get 2-vertex threads,

1
src/gallium/drivers/i965/brw_winsys.h
View File

@ -44,7 +44,6 @@ struct brw_winsys_screen;
struct brw_winsys_buffer {
struct pipe_reference reference;
struct brw_winsys_screen *sws;
unsigned *offset;
unsigned size;
};

2
src/gallium/drivers/i965/brw_wm_sampler_state.c
View File

@ -87,7 +87,7 @@ brw_wm_sampler_populate_key(struct brw_context *brw,
entry->ss0 = sampler->ss0;
entry->ss1 = sampler->ss1;
entry->ss2.default_color_pointer = brw->wm.sdc_bo[i]->offset[0] >> 5; /* reloc */
entry->ss2.default_color_pointer = 0; /* reloc */
entry->ss3 = sampler->ss3;
/* Cube-maps on 965 and later must use the same wrap mode for all 3

13
src/gallium/drivers/i965/brw_wm_state.c
View File

@ -149,7 +149,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
memset(&wm, 0, sizeof(wm));
wm.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
wm.thread0.kernel_start_pointer = brw->wm.prog_bo->offset[0] >> 6; /* reloc */
wm.thread0.kernel_start_pointer = 0; /* reloc */
wm.thread1.depth_coef_urb_read_offset = 1;
wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
@ -159,8 +159,7 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
wm.thread1.binding_table_entry_count = key->nr_surfaces;
if (key->total_scratch != 0) {
wm.thread2.scratch_space_base_pointer =
brw->wm.scratch_bo->offset[0] >> 10; /* reloc */
wm.thread2.scratch_space_base_pointer = 0; /* reloc */
wm.thread2.per_thread_scratch_space = key->total_scratch / 1024 - 1;
} else {
wm.thread2.scratch_space_base_pointer = 0;
@ -178,12 +177,8 @@ wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
else
wm.wm4.sampler_count = (key->sampler_count + 1) / 4;
if (brw->wm.sampler_bo != NULL) {
/* reloc */
wm.wm4.sampler_state_pointer = brw->wm.sampler_bo->offset[0] >> 5;
} else {
wm.wm4.sampler_state_pointer = 0;
}
/* reloc */
wm.wm4.sampler_state_pointer = 0;
wm.wm5.program_uses_depth = key->uses_depth;
wm.wm5.program_computes_depth = key->computes_depth;

7
src/gallium/drivers/i965/brw_wm_surface_state.c
View File

@ -130,7 +130,7 @@ brw_update_render_surface(struct brw_context *brw,
*/
ret = brw->sws->bo_emit_reloc(*bo_out,
BRW_USAGE_RENDER_TARGET,
ss.ss1.base_addr - surface->bo->offset[0], /* XXX */
0,
offsetof(struct brw_surface_state, ss1),
surface->bo);
if (ret)
@ -167,8 +167,11 @@ brw_wm_get_binding_table(struct brw_context *brw,
bo_out))
return PIPE_OK;
/* Upload zero data, will all be overwitten with relocation
* offsets:
*/
for (i = 0; i < brw->wm.nr_surfaces; i++)
data[i] = brw->wm.surf_bo[i]->offset[0];
data[i] = 0;
ret = brw_upload_cache( &brw->surface_cache, BRW_SS_SURF_BIND,
NULL, 0,

1
src/gallium/winsys/drm/i965/xlib/xlib_i965.c
View File

@ -168,7 +168,6 @@ xlib_brw_bo_alloc( struct brw_winsys_screen *sws,
buf->offset = align(xbw->used, alignment);
buf->type = type;
buf->virtual = MALLOC(size);
buf->base.offset = &buf->offset; /* hmm, cheesy */
buf->base.size = size;
buf->base.sws = sws;