pan/bi: Align spilled registers on Valhall
Required to support packed addressing correctly. Fixes (with spilling forced): dEQP-GLES2.functional.shaders.random.trigonometric.vertex.20 Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16314>
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@ -591,6 +591,14 @@ bi_register_allocate(bi_context *ctx)
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if (spill_node == -1)
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unreachable("Failed to choose spill node\n");
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/* By default, we use packed TLS addressing on Valhall.
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* We cannot cross 16 byte boundaries with packed TLS
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* addressing. Align to ensure this doesn't happen. This
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* could be optimized a bit.
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*/
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if (ctx->arch >= 9)
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spill_count = ALIGN_POT(spill_count, 16);
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spill_count += bi_spill_register(ctx,
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bi_node_to_index(spill_node, bi_max_temp(ctx)),
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spill_count);
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