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pan/bi: Align spilled registers on Valhall 

Required to support packed addressing correctly. Fixes (with spilling forced):

dEQP-GLES2.functional.shaders.random.trigonometric.vertex.20

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16314>
This commit is contained in:
Alyssa Rosenzweig 2022-05-03 17:01:24 -04:00 committed by Marge Bot
parent 040a3ef24e
commit 961b18ccbc
1 changed files with 8 additions and 0 deletions
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8
src/panfrost/bifrost/bi_ra.c
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@ -591,6 +591,14 @@ bi_register_allocate(bi_context *ctx)
if (spill_node == -1)
unreachable("Failed to choose spill node\n");
/* By default, we use packed TLS addressing on Valhall.
* We cannot cross 16 byte boundaries with packed TLS
* addressing. Align to ensure this doesn't happen. This
* could be optimized a bit.
*/
if (ctx->arch >= 9)
spill_count = ALIGN_POT(spill_count, 16);
spill_count += bi_spill_register(ctx,
bi_node_to_index(spill_node, bi_max_temp(ctx)),
spill_count);