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pan/va: Fix BLEND instruction 

There's only one staging register, the other register is just offset due to the
Msg64 source.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15364>
This commit is contained in:
Alyssa Rosenzweig 2022-03-04 20:03:08 -05:00 committed by Marge Bot
parent c7e8e8b319
commit 95b7908d2d
2 changed files with 4 additions and 4 deletions
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4
src/panfrost/bifrost/valhall/ISA.xml
View File

@ -1203,8 +1203,8 @@
shaders efficiently and without shader variants.
</desc>
<sr read="true"/>
<sr write="true" count="1" flags="false"/>
<src>Blend descriptor</src>
<src size="64">Blend descriptor</src>
<src>Sample coverage</src>
<imm name="target" start="8" size="8"/>
<slot/>
<sr_count/>

4
src/panfrost/bifrost/valhall/test/assembler-cases.txt
View File

@ -50,7 +50,7 @@ e6 00 00 00 00 c1 91 06 MOV.i32.id r1, core_id
c0 00 00 00 00 f6 10 01 IADD_IMM.i32 r54, 0x0, #0x0
3c d0 ea 00 02 bc 7d 68 ATEST.td @r60, r60, 0x3F800000, atest_datum
40 db 05 04 00 c1 a1 00 MKVEC.v2i16 r1, `r0.h00, 0x3C000000.h10
f0 00 3c 33 04 40 7f 78 BLEND.slot0.v4.f16.return @r0:r1, @r60, blend_descriptor_0_x, target:0x0
f0 00 3c 33 04 40 7f 78 BLEND.slot0.v4.f16.return @r0:r1, blend_descriptor_0_x, r60, target:0x0
7b 0d 00 40 04 84 5e 08 LEA_BUF_IMM.slot1.wait0 @r4:r5, `r59, table:0xD, index:0x0
00 dd c0 08 14 c2 b2 00 FMA.f32 r2, r0, 0x44000000.neg.h1, 0x0.neg
41 88 c0 00 04 c1 b2 00 FMA.f32 r1, `r1, u8, 0x0.neg
@ -210,7 +210,7 @@ c0 00 00 00 00 c9 10 01 IADD_IMM.i32 r9, 0x0, #0x0
41 3f 00 08 00 c1 a4 00 FADD.f32 r1, `r1, r63.h1
40 7f 00 04 00 c0 a4 00 FADD.f32 r0, `r0, `r63.h0
42 49 00 04 00 c2 a4 48 FADD.f32.barrier r2, `r2, `r9.h0
f0 00 3c 32 08 40 7f 78 BLEND.slot0.v4.f32.return @r0:r1:r2:r3, @r60, blend_descriptor_0_x, target:0x0
f0 00 3c 32 08 40 7f 78 BLEND.slot0.v4.f32.return @r0:r1:r2:r3, blend_descriptor_0_x, r60, target:0x0
c0 00 00 00 00 f6 10 01 IADD_IMM.i32 r54, 0x0, #0x0
c0 f1 00 00 10 c1 2f 08 BRANCHZI.eq.absolute.wait0 0x0, blend_descriptor_0_y
80 00 c0 17 34 7c 25 01 TEX_FETCH.slot0.f.32.2d @r0:r1:r2:r3, @r60:r61, u0