freedreno/ir3+isa: Cleanup bindless cat5 samp/tex encoding
Don't let the way they are encoded at the isa level leak thru to the ir3 level. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>
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@ -1117,7 +1117,7 @@ struct tex_src_info {
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/* For prefetch */
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unsigned tex_base, samp_base, tex_idx, samp_idx;
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/* For normal tex instructions */
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unsigned base, combined_idx, a1_val, flags;
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unsigned base, a1_val, flags;
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struct ir3_instruction *samp_tex;
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};
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@ -1150,11 +1150,9 @@ get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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if (info.tex_idx < 16) {
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/* Everything fits within the instruction */
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info.base = info.tex_base;
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info.combined_idx = info.samp_idx | (info.tex_idx << 4);
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} else {
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info.base = info.tex_base;
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info.a1_val = info.tex_idx << 3;
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info.combined_idx = 0;
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info.flags |= IR3_INSTR_A1EN;
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}
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info.samp_tex = NULL;
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@ -1200,7 +1198,8 @@ emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
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}
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if (info.flags & IR3_INSTR_B) {
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sam->cat5.tex_base = info.base;
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sam->cat5.samp = info.combined_idx;
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sam->cat5.samp = info.samp_idx;
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sam->cat5.tex = info.tex_idx;
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}
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return sam;
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}
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@ -2305,11 +2304,9 @@ get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
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info.tex_base == info.samp_base)) {
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/* Everything fits within the instruction */
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info.base = info.tex_base;
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info.combined_idx = info.samp_idx | (info.tex_idx << 4);
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} else {
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info.base = info.tex_base;
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info.a1_val = info.tex_idx << 3 | info.samp_base;
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info.combined_idx = info.samp_idx;
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info.flags |= IR3_INSTR_A1EN;
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}
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info.samp_tex = NULL;
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@ -984,7 +984,7 @@ cat5_flags:
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| cat5_flag cat5_flags
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cat5_samp: T_SAMP { instr->cat5.samp = $1; }
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cat5_tex: T_TEX { if (instr->flags & IR3_INSTR_B) instr->cat5.samp |= ($1 << 4); else instr->cat5.tex = $1; }
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cat5_tex: T_TEX { instr->cat5.tex = $1; }
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cat5_type: '(' type ')' { instr->cat5.type = $2; }
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cat5_a1: src_reg { instr->flags |= IR3_INSTR_A1EN; }
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@ -340,14 +340,8 @@ print_instr(struct log_stream *stream, struct ir3_instruction *instr, int lvl)
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}
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if (is_tex(instr) && !(instr->flags & IR3_INSTR_S2EN)) {
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if (!!(instr->flags & IR3_INSTR_B)) {
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if (!!(instr->flags & IR3_INSTR_A1EN)) {
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if (!!(instr->flags & IR3_INSTR_B) && !!(instr->flags & IR3_INSTR_A1EN)) {
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mesa_log_stream_printf(stream, ", s#%d", instr->cat5.samp);
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} else {
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mesa_log_stream_printf(stream, ", s#%d, t#%d",
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instr->cat5.samp & 0xf,
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instr->cat5.samp >> 4);
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}
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} else {
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mesa_log_stream_printf(stream, ", s#%d, t#%d", instr->cat5.samp,
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instr->cat5.tex);
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@ -481,12 +481,7 @@ SOFTWARE.
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<display/>
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<assert low="0" high="3">0000</assert>
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<encode type="struct ir3_instruction *">
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<!--
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TODO properly decouple the encoding from ir3 IR in this
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case.. the IR has no business knowing how this gets
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encoded into "SRC3"..
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-->
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<map name="TEX">src->cat5.samp >> 4</map>
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<map name="TEX">src->cat5.tex</map>
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</encode>
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</bitset>
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