aco: use full-register instructions to implement subdword packing on GFX6/7
On GFX6/7, there are no SDWA instructions. Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5226>
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@ -1042,6 +1042,29 @@ bool do_copy(lower_context* ctx, Builder& bld, const copy_operation& copy, bool
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*preserve_scc = true;
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} else if (def.bytes() == 8 && def.getTemp().type() == RegType::sgpr) {
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bld.sop1(aco_opcode::s_mov_b64, def, Operand(op.physReg(), s2));
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} else if (def.regClass().is_subdword() && ctx->program->chip_class < GFX8) {
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if (op.physReg().byte()) {
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assert(def.physReg().byte() == 0);
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bld.vop2(aco_opcode::v_lshrrev_b32, def, Operand(op.physReg().byte() * 8), op);
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} else if (def.physReg().byte() == 2) {
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assert(op.physReg().byte() == 0);
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/* preserve the target's lower half */
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def = Definition(def.physReg().advance(-2), v1);
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bld.vop2(aco_opcode::v_and_b32, Definition(op.physReg(), v1), Operand(0xFFFFu), op);
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if (def.physReg().reg() != op.physReg().reg())
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bld.vop2(aco_opcode::v_and_b32, def, Operand(0xFFFFu), Operand(def.physReg(), v2b));
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bld.vop2(aco_opcode::v_cvt_pk_u16_u32, def, Operand(def.physReg(), v2b), op);
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} else if (def.physReg().byte()) {
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unsigned bits = def.physReg().byte() * 8;
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assert(op.physReg().byte() == 0);
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def = Definition(def.physReg().advance(-def.physReg().byte()), v1);
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bld.vop2(aco_opcode::v_and_b32, def, Operand((1 << bits) - 1u), Operand(def.physReg(), op.regClass()));
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bld.vop2(aco_opcode::v_lshlrev_b32, Definition(op.physReg(), def.regClass()), Operand(bits), op);
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bld.vop2(aco_opcode::v_or_b32, def, Operand(def.physReg(), op.regClass()), op);
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bld.vop2(aco_opcode::v_lshrrev_b32, Definition(op.physReg(), def.regClass()), Operand(bits), op);
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} else {
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bld.vop1(aco_opcode::v_mov_b32, def, op);
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}
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} else {
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bld.copy(def, op);
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}
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@ -1092,7 +1115,8 @@ void do_swap(lower_context *ctx, Builder& bld, const copy_operation& copy, bool
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Definition op_as_def = Definition(op.physReg(), op.regClass());
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if (ctx->program->chip_class >= GFX9 && def.regClass() == v1) {
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bld.vop1(aco_opcode::v_swap_b32, def, op_as_def, op, def_as_op);
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} else if (def.regClass() == v1) {
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} else if (def.regClass() == v1 || (def.regClass().is_subdword() && ctx->program->chip_class < GFX8)) {
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assert(def.physReg().byte() == 0 && op.physReg().byte() == 0);
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bld.vop2(aco_opcode::v_xor_b32, op_as_def, op, def_as_op);
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bld.vop2(aco_opcode::v_xor_b32, def, op, def_as_op);
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bld.vop2(aco_opcode::v_xor_b32, op_as_def, op, def_as_op);
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