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i965: fix PIPE_CONTROL command for gen6. 

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Zou Nan hai 2010-05-18 16:22:40 +08:00 committed by Eric Anholt
parent e6d8b4090f
commit 9390af0d96
1 changed files with 10 additions and 1 deletions
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11
src/mesa/drivers/dri/intel/intel_batchbuffer.c
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@ -275,7 +275,16 @@ intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch)
{
struct intel_context *intel = batch->intel;
if (intel->gen >= 4) {
if (intel->gen >= 6) {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL);
OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH |
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_NO_WRITE);
OUT_BATCH(0); /* write address */
OUT_BATCH(0); /* write data */
ADVANCE_BATCH();
} else if (intel->gen >= 4) {
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_PIPE_CONTROL |
PIPE_CONTROL_WRITE_FLUSH |