nvc0/ir: add support for new TGSI double opcodes
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ilia Mirkin
parent
ef8f09be33
commit
93812dc10a
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@ -297,6 +297,30 @@ unsigned int Instruction::srcMask(unsigned int s) const
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if (mask & 4) x |= 0x3;
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return x;
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}
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case TGSI_OPCODE_D2I:
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case TGSI_OPCODE_D2U:
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case TGSI_OPCODE_D2F:
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case TGSI_OPCODE_DSLT:
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case TGSI_OPCODE_DSGE:
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case TGSI_OPCODE_DSEQ:
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case TGSI_OPCODE_DSNE:
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switch (util_bitcount(mask)) {
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case 1: return 0x3;
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case 2: return 0xf;
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default:
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assert(!"unexpected mask");
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return 0xf;
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}
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case TGSI_OPCODE_I2D:
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case TGSI_OPCODE_U2D:
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case TGSI_OPCODE_F2D: {
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unsigned int x = 0;
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if ((mask & 0x3) == 0x3)
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x |= 1;
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if ((mask & 0xc) == 0xc)
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x |= 2;
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return x;
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}
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default:
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break;
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}
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@ -397,6 +421,7 @@ nv50_ir::DataType Instruction::inferSrcType() const
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case TGSI_OPCODE_XOR:
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case TGSI_OPCODE_NOT:
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case TGSI_OPCODE_U2F:
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case TGSI_OPCODE_U2D:
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case TGSI_OPCODE_UADD:
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case TGSI_OPCODE_UDIV:
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case TGSI_OPCODE_UMOD:
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@ -423,6 +448,7 @@ nv50_ir::DataType Instruction::inferSrcType() const
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case TGSI_OPCODE_UMSB:
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return nv50_ir::TYPE_U32;
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case TGSI_OPCODE_I2F:
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case TGSI_OPCODE_I2D:
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case TGSI_OPCODE_IDIV:
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case TGSI_OPCODE_IMUL_HI:
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case TGSI_OPCODE_IMAX:
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@ -441,6 +467,29 @@ nv50_ir::DataType Instruction::inferSrcType() const
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case TGSI_OPCODE_IBFE:
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case TGSI_OPCODE_IMSB:
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return nv50_ir::TYPE_S32;
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case TGSI_OPCODE_D2F:
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case TGSI_OPCODE_D2I:
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case TGSI_OPCODE_D2U:
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case TGSI_OPCODE_DABS:
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case TGSI_OPCODE_DNEG:
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case TGSI_OPCODE_DADD:
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case TGSI_OPCODE_DMUL:
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case TGSI_OPCODE_DMAX:
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case TGSI_OPCODE_DMIN:
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case TGSI_OPCODE_DSLT:
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case TGSI_OPCODE_DSGE:
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case TGSI_OPCODE_DSEQ:
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case TGSI_OPCODE_DSNE:
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case TGSI_OPCODE_DRCP:
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case TGSI_OPCODE_DSQRT:
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case TGSI_OPCODE_DMAD:
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case TGSI_OPCODE_DFRAC:
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case TGSI_OPCODE_DRSQ:
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case TGSI_OPCODE_DTRUNC:
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case TGSI_OPCODE_DCEIL:
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case TGSI_OPCODE_DFLR:
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case TGSI_OPCODE_DROUND:
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return nv50_ir::TYPE_F64;
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default:
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return nv50_ir::TYPE_F32;
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}
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@ -449,16 +498,27 @@ nv50_ir::DataType Instruction::inferSrcType() const
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nv50_ir::DataType Instruction::inferDstType() const
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{
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switch (getOpcode()) {
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case TGSI_OPCODE_D2U:
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case TGSI_OPCODE_F2U: return nv50_ir::TYPE_U32;
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case TGSI_OPCODE_D2I:
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case TGSI_OPCODE_F2I: return nv50_ir::TYPE_S32;
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case TGSI_OPCODE_FSEQ:
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case TGSI_OPCODE_FSGE:
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case TGSI_OPCODE_FSLT:
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case TGSI_OPCODE_FSNE:
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case TGSI_OPCODE_DSEQ:
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case TGSI_OPCODE_DSGE:
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case TGSI_OPCODE_DSLT:
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case TGSI_OPCODE_DSNE:
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return nv50_ir::TYPE_U32;
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case TGSI_OPCODE_I2F:
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case TGSI_OPCODE_U2F:
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case TGSI_OPCODE_D2F:
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return nv50_ir::TYPE_F32;
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case TGSI_OPCODE_I2D:
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case TGSI_OPCODE_U2D:
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case TGSI_OPCODE_F2D:
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return nv50_ir::TYPE_F64;
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default:
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return inferSrcType();
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}
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@ -473,6 +533,7 @@ nv50_ir::CondCode Instruction::getSetCond() const
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case TGSI_OPCODE_ISLT:
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case TGSI_OPCODE_USLT:
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case TGSI_OPCODE_FSLT:
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case TGSI_OPCODE_DSLT:
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return CC_LT;
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case TGSI_OPCODE_SLE:
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return CC_LE;
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@ -480,15 +541,18 @@ nv50_ir::CondCode Instruction::getSetCond() const
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case TGSI_OPCODE_ISGE:
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case TGSI_OPCODE_USGE:
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case TGSI_OPCODE_FSGE:
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case TGSI_OPCODE_DSGE:
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return CC_GE;
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case TGSI_OPCODE_SGT:
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return CC_GT;
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case TGSI_OPCODE_SEQ:
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case TGSI_OPCODE_USEQ:
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case TGSI_OPCODE_FSEQ:
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case TGSI_OPCODE_DSEQ:
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return CC_EQ;
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case TGSI_OPCODE_SNE:
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case TGSI_OPCODE_FSNE:
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case TGSI_OPCODE_DSNE:
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return CC_NEU;
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case TGSI_OPCODE_USNE:
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return CC_NE;
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@ -601,6 +665,29 @@ static nv50_ir::operation translateOpcode(uint opcode)
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NV50_IR_OPCODE_CASE(USLT, SET);
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NV50_IR_OPCODE_CASE(USNE, SET);
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NV50_IR_OPCODE_CASE(DABS, ABS);
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NV50_IR_OPCODE_CASE(DNEG, NEG);
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NV50_IR_OPCODE_CASE(DADD, ADD);
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NV50_IR_OPCODE_CASE(DMUL, MUL);
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NV50_IR_OPCODE_CASE(DMAX, MAX);
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NV50_IR_OPCODE_CASE(DMIN, MIN);
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NV50_IR_OPCODE_CASE(DSLT, SET);
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NV50_IR_OPCODE_CASE(DSGE, SET);
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NV50_IR_OPCODE_CASE(DSEQ, SET);
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NV50_IR_OPCODE_CASE(DSNE, SET);
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NV50_IR_OPCODE_CASE(DRCP, RCP);
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NV50_IR_OPCODE_CASE(DSQRT, SQRT);
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NV50_IR_OPCODE_CASE(DMAD, MAD);
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NV50_IR_OPCODE_CASE(D2I, CVT);
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NV50_IR_OPCODE_CASE(D2U, CVT);
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NV50_IR_OPCODE_CASE(I2D, CVT);
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NV50_IR_OPCODE_CASE(U2D, CVT);
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NV50_IR_OPCODE_CASE(DRSQ, RSQ);
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NV50_IR_OPCODE_CASE(DTRUNC, TRUNC);
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NV50_IR_OPCODE_CASE(DCEIL, CEIL);
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NV50_IR_OPCODE_CASE(DFLR, FLOOR);
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NV50_IR_OPCODE_CASE(DROUND, CVT);
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NV50_IR_OPCODE_CASE(IMUL_HI, MUL);
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NV50_IR_OPCODE_CASE(UMUL_HI, MUL);
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@ -2880,6 +2967,155 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
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case TGSI_OPCODE_INTERP_OFFSET:
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handleINTERP(dst0);
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break;
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case TGSI_OPCODE_D2I:
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case TGSI_OPCODE_D2U:
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case TGSI_OPCODE_D2F: {
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int pos = 0;
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FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
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Value *dreg = getSSA(8);
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src0 = fetchSrc(0, pos);
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src1 = fetchSrc(0, pos + 1);
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mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1);
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mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg);
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pos += 2;
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}
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break;
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}
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case TGSI_OPCODE_I2D:
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case TGSI_OPCODE_U2D:
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case TGSI_OPCODE_F2D:
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FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
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Value *dreg = getSSA(8);
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mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2));
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mkSplit(&dst0[c], 4, dreg);
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c++;
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}
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break;
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case TGSI_OPCODE_DABS:
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case TGSI_OPCODE_DNEG:
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case TGSI_OPCODE_DRCP:
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case TGSI_OPCODE_DSQRT:
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case TGSI_OPCODE_DRSQ:
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case TGSI_OPCODE_DTRUNC:
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case TGSI_OPCODE_DCEIL:
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case TGSI_OPCODE_DFLR:
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FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
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src0 = getSSA(8);
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Value *dst = getSSA(8), *tmp[2];
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tmp[0] = fetchSrc(0, c);
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tmp[1] = fetchSrc(0, c + 1);
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mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
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mkOp1(op, dstTy, dst, src0);
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mkSplit(&dst0[c], 4, dst);
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c++;
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}
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break;
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case TGSI_OPCODE_DFRAC:
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FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
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src0 = getSSA(8);
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Value *dst = getSSA(8), *tmp[2];
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tmp[0] = fetchSrc(0, c);
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tmp[1] = fetchSrc(0, c + 1);
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mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
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mkOp1(OP_FLOOR, TYPE_F64, dst, src0);
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mkOp2(OP_SUB, TYPE_F64, dst, src0, dst);
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mkSplit(&dst0[c], 4, dst);
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c++;
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}
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break;
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case TGSI_OPCODE_DSLT:
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case TGSI_OPCODE_DSGE:
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case TGSI_OPCODE_DSEQ:
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case TGSI_OPCODE_DSNE: {
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int pos = 0;
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FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
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Value *tmp[2];
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src0 = getSSA(8);
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src1 = getSSA(8);
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tmp[0] = fetchSrc(0, pos);
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tmp[1] = fetchSrc(0, pos + 1);
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mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
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tmp[0] = fetchSrc(1, pos);
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tmp[1] = fetchSrc(1, pos + 1);
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mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
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mkCmp(op, tgsi.getSetCond(), dstTy, dst0[c], srcTy, src0, src1);
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pos += 2;
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}
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break;
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}
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case TGSI_OPCODE_DADD:
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case TGSI_OPCODE_DMUL:
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case TGSI_OPCODE_DMAX:
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case TGSI_OPCODE_DMIN:
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FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
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src0 = getSSA(8);
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src1 = getSSA(8);
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Value *dst = getSSA(8), *tmp[2];
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tmp[0] = fetchSrc(0, c);
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tmp[1] = fetchSrc(0, c + 1);
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mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
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tmp[0] = fetchSrc(1, c);
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tmp[1] = fetchSrc(1, c + 1);
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mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
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mkOp2(op, dstTy, dst, src0, src1);
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mkSplit(&dst0[c], 4, dst);
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c++;
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}
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break;
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case TGSI_OPCODE_DMAD:
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FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
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src0 = getSSA(8);
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src1 = getSSA(8);
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src2 = getSSA(8);
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Value *dst = getSSA(8), *tmp[2];
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tmp[0] = fetchSrc(0, c);
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tmp[1] = fetchSrc(0, c + 1);
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mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
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tmp[0] = fetchSrc(1, c);
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tmp[1] = fetchSrc(1, c + 1);
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mkOp2(OP_MERGE, TYPE_U64, src1, tmp[0], tmp[1]);
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tmp[0] = fetchSrc(2, c);
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tmp[1] = fetchSrc(2, c + 1);
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mkOp2(OP_MERGE, TYPE_U64, src2, tmp[0], tmp[1]);
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mkOp3(op, dstTy, dst, src0, src1, src2);
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mkSplit(&dst0[c], 4, dst);
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c++;
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}
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break;
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case TGSI_OPCODE_DROUND:
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FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
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src0 = getSSA(8);
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Value *dst = getSSA(8), *tmp[2];
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tmp[0] = fetchSrc(0, c);
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tmp[1] = fetchSrc(0, c + 1);
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mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
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mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F64, src0)
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->rnd = ROUND_NI;
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mkSplit(&dst0[c], 4, dst);
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c++;
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}
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break;
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case TGSI_OPCODE_DSSG:
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FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) {
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src0 = getSSA(8);
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Value *dst = getSSA(8), *dstF32 = getSSA(), *tmp[2];
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tmp[0] = fetchSrc(0, c);
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tmp[1] = fetchSrc(0, c + 1);
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mkOp2(OP_MERGE, TYPE_U64, src0, tmp[0], tmp[1]);
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val0 = getScratch();
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val1 = getScratch();
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// The zero is wrong here since it's only 32-bit, but it works out in
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// the end since it gets replaced with $r63.
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mkCmp(OP_SET, CC_GT, TYPE_F32, val0, TYPE_F64, src0, zero);
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mkCmp(OP_SET, CC_LT, TYPE_F32, val1, TYPE_F64, src0, zero);
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mkOp2(OP_SUB, TYPE_F32, dstF32, val0, val1);
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mkCvt(OP_CVT, TYPE_F64, dst, TYPE_F32, dstF32);
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mkSplit(&dst0[c], 4, dst);
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c++;
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}
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break;
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default:
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ERROR("unhandled TGSI opcode: %u\n", tgsi.getOpcode());
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assert(0);
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