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freedreno/ir3: fix neverball assert in case of unused VS inputs 

The logic to ensure VS and BS inputs are aligned wasn't accounting for
unused inputs in VS.  This *usually* doesn't happen, but it seems it
can in the case of ARB programs?

Fixes assert:
```
fd6_program_create: Assertion `bs->inputs[i].regid == vs->inputs[i].regid' failed.
```

Fixes: 882d53d8e3 ("freedreno/ir3+a6xx: same VBO state for draw/binning")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
This commit is contained in:
Rob Clark 2019-12-03 13:44:35 -08:00
parent 4e47c205b9
commit 937b905569
3 changed files with 19 additions and 7 deletions
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4
src/freedreno/ir3/ir3.h
View File

@ -614,6 +614,10 @@ static inline uint32_t reg_comp(struct ir3_register *reg)
return reg->num & 0x3;
}
#define INVALID_REG regid(63, 0)
#define VALIDREG(r) ((r) != INVALID_REG)
#define CONDREG(r, val) COND(VALIDREG(r), (val))
static inline bool is_flow(struct ir3_instruction *instr)
{
return (opc_cat(instr->opc) == 0);

19
src/freedreno/ir3/ir3_compiler_nir.c
View File

@ -3472,9 +3472,9 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
*/
for (unsigned i = 0; i < so->inputs_count; i++)
so->inputs[i].regid = regid(63, 0);
so->inputs[i].regid = INVALID_REG;
for (unsigned i = 0; i < so->outputs_count; i++)
so->outputs[i].regid = regid(63, 0);
so->outputs[i].regid = INVALID_REG;
struct ir3_instruction *out;
foreach_output(out, ir) {
@ -3490,8 +3490,19 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
assert(in->opc == OPC_META_INPUT);
unsigned inidx = in->input.inidx;
so->inputs[inidx].regid = in->regs[0]->num;
so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
if (pre_assign_inputs) {
if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
compile_assert(ctx, in->regs[0]->num ==
so->nonbinning->inputs[inidx].regid);
compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
so->nonbinning->inputs[inidx].half);
}
so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
} else {
so->inputs[inidx].regid = in->regs[0]->num;
so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
}
}
if (ctx->astc_srgb)

3
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View File

@ -256,9 +256,6 @@ setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *stat
OUT_RING(ring, state->fs->image_mapping.num_ibo);
}
#define VALIDREG(r) ((r) != regid(63,0))
#define CONDREG(r, val) COND(VALIDREG(r), (val))
static inline uint32_t
next_regid(uint32_t reg, uint32_t increment)
{