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ir3: Only use per-wave pvtmem layout for compute 

The blob seems to do this since a630, and it fixes
spec@glsl-1.30@execution@fs-large-local-array on a650.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10922>
This commit is contained in:
Connor Abbott 2021-05-20 18:30:12 +02:00 committed by Marge Bot
parent 0ab01f4215
commit 9350900fcd
1 changed files with 6 additions and 3 deletions
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9
src/freedreno/ir3/ir3_shader.c
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@ -176,10 +176,13 @@ void * ir3_shader_assemble(struct ir3_shader_variant *v)
if (compiler->gpu_id >= 400)
v->constlen = align(v->constlen, 4);
/* Use the per-wave layout by default on a6xx. It should result in better
* performance when loads/stores are to a uniform index.
/* Use the per-wave layout by default on a6xx for compute shaders. It
* should result in better performance when loads/stores are to a uniform
* index.
*/
v->pvtmem_per_wave = compiler->gpu_id >= 600 && !info->multi_dword_ldp_stp;
v->pvtmem_per_wave =
compiler->gpu_id >= 600 && !info->multi_dword_ldp_stp &&
v->type == MESA_SHADER_COMPUTE;
fixup_regfootprint(v);