i965: Only flush the batchbuffer if we need to zero the SO offsets
If we don't have pipelined register access (e.g. Haswell before kernel v4.2), then we can only implement EXT_transform_feedback by reseting the SO offsets *between* batches. However, if we do have pipelined access to the SO registers on gen7, we can simply emit an inline reset of the SO registers without a full batch flush. v2 [by Ken]: Simplify after recent kernel feature detection changes. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -352,10 +352,6 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
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assert(brw->gen == 7);
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/* Reset the SO buffer offsets to 0. */
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intel_batchbuffer_flush(brw);
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brw->batch.needs_sol_reset = true;
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/* We're about to lose the information needed to compute the number of
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* vertices written during the last Begin/EndTransformFeedback section,
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* so we can't delay it any further.
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@ -370,6 +366,20 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
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/* Store the starting value of the SO_NUM_PRIMS_WRITTEN counters. */
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brw_save_primitives_written_counters(brw, brw_obj);
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/* Reset the SO buffer offsets to 0. */
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if (!can_do_pipelined_register_writes(brw->screen)) {
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intel_batchbuffer_flush(brw);
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brw->batch.needs_sol_reset = true;
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} else {
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for (int i = 0; i < 4; i++) {
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BEGIN_BATCH(3);
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OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
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OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
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OUT_BATCH(0);
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ADVANCE_BATCH();
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}
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}
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brw_obj->primitive_mode = mode;
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}
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