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i965: Only flush the batchbuffer if we need to zero the SO offsets 

If we don't have pipelined register access (e.g. Haswell before kernel
v4.2), then we can only implement EXT_transform_feedback by reseting the
SO offsets *between* batches. However, if we do have pipelined access to
the SO registers on gen7, we can simply emit an inline reset of the SO
registers without a full batch flush.

v2 [by Ken]: Simplify after recent kernel feature detection changes.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Chris Wilson 2017-01-10 21:23:26 +00:00 committed by Kenneth Graunke
parent 7ad692d8e2
commit 92281b2c7f
1 changed files with 14 additions and 4 deletions
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18
src/mesa/drivers/dri/i965/gen7_sol_state.c
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@ -352,10 +352,6 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
assert(brw->gen == 7);
/* Reset the SO buffer offsets to 0. */
intel_batchbuffer_flush(brw);
brw->batch.needs_sol_reset = true;
/* We're about to lose the information needed to compute the number of
* vertices written during the last Begin/EndTransformFeedback section,
* so we can't delay it any further.
@ -370,6 +366,20 @@ gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
/* Store the starting value of the SO_NUM_PRIMS_WRITTEN counters. */
brw_save_primitives_written_counters(brw, brw_obj);
/* Reset the SO buffer offsets to 0. */
if (!can_do_pipelined_register_writes(brw->screen)) {
intel_batchbuffer_flush(brw);
brw->batch.needs_sol_reset = true;
} else {
for (int i = 0; i < 4; i++) {
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
OUT_BATCH(GEN7_SO_WRITE_OFFSET(i));
OUT_BATCH(0);
ADVANCE_BATCH();
}
}
brw_obj->primitive_mode = mode;
}