nvc0: bind shader buffers for compute on Fermi
This is loosely based on 3D. Shader buffers are bound on c15 (the driver constbuf) at offset 0x200. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
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@ -212,6 +212,38 @@ nvc0_compute_validate_driverconst(struct nvc0_context *nvc0)
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nvc0->dirty |= NVC0_NEW_DRIVERCONST;
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}
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static void
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nvc0_compute_validate_buffers(struct nvc0_context *nvc0)
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{
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struct nouveau_pushbuf *push = nvc0->base.pushbuf;
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const int s = 5;
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int i;
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BEGIN_NVC0(push, NVC0_COMPUTE(CB_SIZE), 3);
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PUSH_DATA (push, 1024);
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PUSH_DATAh(push, nvc0->screen->uniform_bo->offset + (6 << 16) + (s << 10));
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PUSH_DATA (push, nvc0->screen->uniform_bo->offset + (6 << 16) + (s << 10));
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BEGIN_1IC0(push, NVC0_COMPUTE(CB_POS), 1 + 4 * NVC0_MAX_BUFFERS);
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PUSH_DATA (push, 512);
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for (i = 0; i < NVC0_MAX_BUFFERS; i++) {
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if (nvc0->buffers[s][i].buffer) {
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struct nv04_resource *res =
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nv04_resource(nvc0->buffers[s][i].buffer);
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PUSH_DATA (push, res->address + nvc0->buffers[s][i].buffer_offset);
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PUSH_DATAh(push, res->address + nvc0->buffers[s][i].buffer_offset);
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PUSH_DATA (push, nvc0->buffers[s][i].buffer_size);
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PUSH_DATA (push, 0);
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BCTX_REFN(nvc0->bufctx_cp, CP_BUF, res, RDWR);
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} else {
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PUSH_DATA (push, 0);
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PUSH_DATA (push, 0);
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PUSH_DATA (push, 0);
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PUSH_DATA (push, 0);
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}
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}
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}
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static bool
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nvc0_compute_state_validate(struct nvc0_context *nvc0)
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{
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@ -221,6 +253,8 @@ nvc0_compute_state_validate(struct nvc0_context *nvc0)
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nvc0_compute_validate_constbufs(nvc0);
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if (nvc0->dirty_cp & NVC0_NEW_CP_DRIVERCONST)
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nvc0_compute_validate_driverconst(nvc0);
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if (nvc0->dirty_cp & NVC0_NEW_CP_BUFFERS)
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nvc0_compute_validate_buffers(nvc0);
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/* TODO: textures, samplers, surfaces, global memory buffers */
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@ -261,12 +261,17 @@ nvc0_invalidate_resource_storage(struct nouveau_context *ctx,
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}
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}
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for (s = 0; s < 5; ++s) {
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for (s = 0; s < 6; ++s) {
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for (i = 0; i < NVC0_MAX_BUFFERS; ++i) {
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if (nvc0->buffers[s][i].buffer == res) {
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nvc0->buffers_dirty[s] |= 1 << i;
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nvc0->dirty |= NVC0_NEW_BUFFERS;
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nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_BUF);
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if (unlikely(s == 5)) {
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nvc0->dirty_cp |= NVC0_NEW_CP_BUFFERS;
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nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
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} else {
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nvc0->dirty |= NVC0_NEW_BUFFERS;
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nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_BUF);
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}
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if (!--ref)
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return ref;
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}
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@ -66,6 +66,7 @@
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#define NVC0_NEW_CP_CONSTBUF (1 << 4)
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#define NVC0_NEW_CP_GLOBALS (1 << 5)
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#define NVC0_NEW_CP_DRIVERCONST (1 << 6)
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#define NVC0_NEW_CP_BUFFERS (1 << 7)
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/* 3d bufctx (during draw_vbo, blit_3d) */
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#define NVC0_BIND_FB 0
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@ -89,7 +90,8 @@
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#define NVC0_BIND_CP_DESC 50
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#define NVC0_BIND_CP_SCREEN 51
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#define NVC0_BIND_CP_QUERY 52
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#define NVC0_BIND_CP_COUNT 53
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#define NVC0_BIND_CP_BUF 53
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#define NVC0_BIND_CP_COUNT 54
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/* bufctx for other operations */
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#define NVC0_BIND_2D 0
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@ -546,6 +546,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
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info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0);
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} else {
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info->io.resInfoCBSlot = 15;
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info->io.suInfoBase = 512;
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}
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info->io.msInfoCBSlot = 0;
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info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS;
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@ -1245,7 +1245,7 @@ nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
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const unsigned mask = ((1 << nr) - 1) << start;
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unsigned i;
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assert(t < 5);
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assert(t < 6);
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if (pbuffers) {
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for (i = start; i < end; ++i) {
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@ -1265,7 +1265,11 @@ nvc0_bind_buffers_range(struct nvc0_context *nvc0, const unsigned t,
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}
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nvc0->buffers_dirty[t] |= mask;
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nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_BUF);
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if (t == 5)
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nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_BUF);
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else
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nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_BUF);
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}
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static void
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@ -1277,7 +1281,10 @@ nvc0_set_shader_buffers(struct pipe_context *pipe,
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const unsigned s = nvc0_shader_stage(shader);
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nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers);
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nvc0_context(pipe)->dirty |= NVC0_NEW_BUFFERS;
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if (s == 5)
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nvc0_context(pipe)->dirty_cp |= NVC0_NEW_CP_BUFFERS;
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else
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nvc0_context(pipe)->dirty |= NVC0_NEW_BUFFERS;
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}
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static inline void
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