radeonsi: reduce the size of si_pm4_state
- the relocs array is unused, remove it - ndw is at most 115 (init), set 140 as the maximum - compute needs 4 buffers per state, graphics only needs 1; set 4 as the maximum Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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@ -145,17 +145,13 @@ unsigned si_pm4_dirty_dw(struct si_context *sctx)
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void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state)
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{
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struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
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for (int i = 0; i < state->nbo; ++i) {
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r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, state->bo[i],
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state->bo_usage[i], state->bo_priority[i]);
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}
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memcpy(&cs->buf[cs->cdw], state->pm4, state->ndw * 4);
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for (int i = 0; i < state->nrelocs; ++i) {
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cs->buf[cs->cdw + state->relocs[i]] += cs->cdw << 2;
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}
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cs->cdw += state->ndw;
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#if SI_TRACE_CS
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@ -29,9 +29,8 @@
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#include "radeon/drm/radeon_winsys.h"
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#define SI_PM4_MAX_DW 256
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#define SI_PM4_MAX_BO 32
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#define SI_PM4_MAX_RELOCS 4
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#define SI_PM4_MAX_DW 140
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#define SI_PM4_MAX_BO 4
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// forward defines
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struct si_context;
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@ -54,10 +53,6 @@ struct si_pm4_state
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enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO];
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enum radeon_bo_priority bo_priority[SI_PM4_MAX_BO];
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/* relocs for shader data */
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unsigned nrelocs;
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unsigned relocs[SI_PM4_MAX_RELOCS];
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bool compute_pkt;
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};
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