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gallium: inline pipe_depth_state to decrease DSA state size by 4 bytes 

Depth and alpha states are now packed together, interleaved somewhat.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7940>
This commit is contained in:
Marek Olšák 2020-12-04 08:37:14 -05:00 committed by Marge Bot
parent d0534cea7f
commit 912ba743b5
59 changed files with 242 additions and 243 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/gallium/auxiliary/driver_trace/tr_dump_state.c
View File

@ -353,13 +353,9 @@ void trace_dump_depth_stencil_alpha_state(const struct pipe_depth_stencil_alpha_
trace_dump_struct_begin("pipe_depth_stencil_alpha_state");
trace_dump_member_begin("depth");
trace_dump_struct_begin("pipe_depth_state");
trace_dump_member(bool, &state->depth, enabled);
trace_dump_member(bool, &state->depth, writemask);
trace_dump_member(uint, &state->depth, func);
trace_dump_struct_end();
trace_dump_member_end();
trace_dump_member(bool, state, depth_enabled);
trace_dump_member(bool, state, depth_writemask);
trace_dump_member(uint, state, depth_func);
trace_dump_member_begin("stencil");
trace_dump_array_begin();

12
src/gallium/auxiliary/util/u_blitter.c
View File

@ -242,9 +242,9 @@ struct blitter_context *util_blitter_create(struct pipe_context *pipe)
ctx->dsa_keep_depth_stencil =
pipe->create_depth_stencil_alpha_state(pipe, &dsa);
dsa.depth.enabled = 1;
dsa.depth.writemask = 1;
dsa.depth.func = PIPE_FUNC_ALWAYS;
dsa.depth_enabled = 1;
dsa.depth_writemask = 1;
dsa.depth_func = PIPE_FUNC_ALWAYS;
ctx->dsa_write_depth_keep_stencil =
pipe->create_depth_stencil_alpha_state(pipe, &dsa);
@ -258,8 +258,8 @@ struct blitter_context *util_blitter_create(struct pipe_context *pipe)
ctx->dsa_write_depth_stencil =
pipe->create_depth_stencil_alpha_state(pipe, &dsa);
dsa.depth.enabled = 0;
dsa.depth.writemask = 0;
dsa.depth_enabled = 0;
dsa.depth_writemask = 0;
ctx->dsa_keep_depth_write_stencil =
pipe->create_depth_stencil_alpha_state(pipe, &dsa);
@ -2802,7 +2802,7 @@ get_stencil_blit_fallback_dsa(struct blitter_context_priv *ctx, unsigned i)
assert(i < ARRAY_SIZE(ctx->dsa_replicate_stencil_bit));
if (!ctx->dsa_replicate_stencil_bit[i]) {
struct pipe_depth_stencil_alpha_state dsa = { 0 };
dsa.depth.func = PIPE_FUNC_ALWAYS;
dsa.depth_func = PIPE_FUNC_ALWAYS;
dsa.stencil[0].enabled = 1;
dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
dsa.stencil[0].fail_op = PIPE_STENCIL_OP_REPLACE;

12
src/gallium/auxiliary/util/u_dump_state.c
View File

@ -521,15 +521,11 @@ util_dump_depth_stencil_alpha_state(FILE *stream, const struct pipe_depth_stenci
util_dump_struct_begin(stream, "pipe_depth_stencil_alpha_state");
util_dump_member_begin(stream, "depth");
util_dump_struct_begin(stream, "pipe_depth_state");
util_dump_member(stream, bool, &state->depth, enabled);
if (state->depth.enabled) {
util_dump_member(stream, bool, &state->depth, writemask);
util_dump_member(stream, enum_func, &state->depth, func);
util_dump_member(stream, bool, state, depth_enabled);
if (state->depth_enabled) {
util_dump_member(stream, bool, state, depth_writemask);
util_dump_member(stream, enum_func, state, depth_func);
}
util_dump_struct_end(stream);
util_dump_member_end(stream);
util_dump_member_begin(stream, "stencil");
util_dump_array_begin(stream);

2
src/gallium/auxiliary/util/u_tests.c
View File

@ -97,7 +97,7 @@ util_set_blend_normal(struct cso_context *cso)
static void
util_set_dsa_disable(struct cso_context *cso)
{
struct pipe_depth_stencil_alpha_state dsa = {{0}};
struct pipe_depth_stencil_alpha_state dsa = {{{0}}};
cso_set_depth_stencil_alpha(cso, &dsa);
}

6
src/gallium/auxiliary/vl/vl_compositor.c
View File

@ -193,9 +193,9 @@ init_pipe_state(struct vl_compositor *c)
c->rast = c->pipe->create_rasterizer_state(c->pipe, &rast);
memset(&dsa, 0, sizeof dsa);
dsa.depth.enabled = 0;
dsa.depth.writemask = 0;
dsa.depth.func = PIPE_FUNC_ALWAYS;
dsa.depth_enabled = 0;
dsa.depth_writemask = 0;
dsa.depth_func = PIPE_FUNC_ALWAYS;
for (i = 0; i < 2; ++i) {
dsa.stencil[i].enabled = 0;
dsa.stencil[i].func = PIPE_FUNC_ALWAYS;

6
src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
View File

@ -862,9 +862,9 @@ init_pipe_state(struct vl_mpeg12_decoder *dec)
assert(dec);
memset(&dsa, 0, sizeof dsa);
dsa.depth.enabled = 0;
dsa.depth.writemask = 0;
dsa.depth.func = PIPE_FUNC_ALWAYS;
dsa.depth_enabled = 0;
dsa.depth_writemask = 0;
dsa.depth_func = PIPE_FUNC_ALWAYS;
for (i = 0; i < 2; ++i) {
dsa.stencil[i].enabled = 0;
dsa.stencil[i].func = PIPE_FUNC_ALWAYS;

6
src/gallium/drivers/d3d12/d3d12_context.cpp
View File

@ -410,9 +410,9 @@ d3d12_create_depth_stencil_alpha_state(struct pipe_context *pctx,
if (!dsa)
return NULL;
if (depth_stencil_alpha->depth.enabled) {
if (depth_stencil_alpha->depth_enabled) {
dsa->desc.DepthEnable = TRUE;
dsa->desc.DepthFunc = compare_op((pipe_compare_func) depth_stencil_alpha->depth.func);
dsa->desc.DepthFunc = compare_op((pipe_compare_func) depth_stencil_alpha->depth_func);
}
/* TODO Add support for GL_depth_bound_tests */
@ -436,7 +436,7 @@ d3d12_create_depth_stencil_alpha_state(struct pipe_context *pctx,
dsa->desc.StencilReadMask = depth_stencil_alpha->stencil[0].valuemask; /* FIXME Back face mask */
dsa->desc.StencilWriteMask = depth_stencil_alpha->stencil[0].writemask; /* FIXME Back face mask */
dsa->desc.DepthWriteMask = (D3D12_DEPTH_WRITE_MASK) depth_stencil_alpha->depth.writemask;
dsa->desc.DepthWriteMask = (D3D12_DEPTH_WRITE_MASK) depth_stencil_alpha->depth_writemask;
return dsa;
}

2
src/gallium/drivers/etnaviv/etnaviv_state.c
View File

@ -710,7 +710,7 @@ etna_update_zsa(struct etna_context *ctx)
new_pe_depth = VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(zsa->z_test_enabled ?
/* compare funcs have 1 to 1 mapping */
zsa_state->depth.func : PIPE_FUNC_ALWAYS) |
zsa_state->depth_func : PIPE_FUNC_ALWAYS) |
COND(zsa->z_write_enabled, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) |
COND(early_z_test, VIVS_PE_DEPTH_CONFIG_EARLY_Z) |
COND(!late_z_write && !late_z_test && !zsa->stencil_enabled,

2
src/gallium/drivers/etnaviv/etnaviv_state.h
View File

@ -34,7 +34,7 @@
static inline bool
etna_depth_enabled(struct etna_context *ctx)
{
return ctx->zsa && ctx->zsa->depth.enabled;
return ctx->zsa && ctx->zsa->depth_enabled;
}
static inline bool

4
src/gallium/drivers/etnaviv/etnaviv_zsa.c
View File

@ -47,8 +47,8 @@ etna_zsa_state_create(struct pipe_context *pctx,
cs->base = *so;
cs->z_test_enabled = so->depth.enabled && so->depth.func != PIPE_FUNC_ALWAYS;
cs->z_write_enabled = so->depth.enabled && so->depth.writemask;
cs->z_test_enabled = so->depth_enabled && so->depth_func != PIPE_FUNC_ALWAYS;
cs->z_write_enabled = so->depth_enabled && so->depth_writemask;
/* XXX does stencil[0] / stencil[1] order depend on rs->front_ccw? */

6
src/gallium/drivers/freedreno/a2xx/fd2_zsa.c
View File

@ -46,12 +46,12 @@ fd2_zsa_state_create(struct pipe_context *pctx,
so->base = *cso;
so->rb_depthcontrol |=
A2XX_RB_DEPTHCONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */
A2XX_RB_DEPTHCONTROL_ZFUNC(cso->depth_func); /* maps 1:1 */
if (cso->depth.enabled)
if (cso->depth_enabled)
so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_ENABLE |
COND(!cso->alpha_enabled, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE);
if (cso->depth.writemask)
if (cso->depth_writemask)
so->rb_depthcontrol |= A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE;
if (cso->stencil[0].enabled) {

6
src/gallium/drivers/freedreno/a3xx/fd3_zsa.c
View File

@ -46,14 +46,14 @@ fd3_zsa_state_create(struct pipe_context *pctx,
so->base = *cso;
so->rb_depth_control |=
A3XX_RB_DEPTH_CONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */
A3XX_RB_DEPTH_CONTROL_ZFUNC(cso->depth_func); /* maps 1:1 */
if (cso->depth.enabled)
if (cso->depth_enabled)
so->rb_depth_control |=
A3XX_RB_DEPTH_CONTROL_Z_ENABLE |
A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE;
if (cso->depth.writemask)
if (cso->depth_writemask)
so->rb_depth_control |= A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE;
if (cso->stencil[0].enabled) {

6
src/gallium/drivers/freedreno/a4xx/fd4_zsa.c
View File

@ -46,14 +46,14 @@ fd4_zsa_state_create(struct pipe_context *pctx,
so->base = *cso;
so->rb_depth_control |=
A4XX_RB_DEPTH_CONTROL_ZFUNC(cso->depth.func); /* maps 1:1 */
A4XX_RB_DEPTH_CONTROL_ZFUNC(cso->depth_func); /* maps 1:1 */
if (cso->depth.enabled)
if (cso->depth_enabled)
so->rb_depth_control |=
A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE;
if (cso->depth.writemask)
if (cso->depth_writemask)
so->rb_depth_control |= A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE;
if (cso->stencil[0].enabled) {

10
src/gallium/drivers/freedreno/a5xx/fd5_zsa.c
View File

@ -45,7 +45,7 @@ fd5_zsa_state_create(struct pipe_context *pctx,
so->base = *cso;
switch (cso->depth.func) {
switch (cso->depth_func) {
case PIPE_FUNC_LESS:
case PIPE_FUNC_LEQUAL:
so->gras_lrz_cntl = A5XX_GRAS_LRZ_CNTL_ENABLE;
@ -62,18 +62,18 @@ fd5_zsa_state_create(struct pipe_context *pctx,
break;
}
if (!(cso->stencil->enabled || cso->alpha_enabled || !cso->depth.writemask))
if (!(cso->stencil->enabled || cso->alpha_enabled || !cso->depth_writemask))
so->lrz_write = true;
so->rb_depth_cntl |=
A5XX_RB_DEPTH_CNTL_ZFUNC(cso->depth.func); /* maps 1:1 */
A5XX_RB_DEPTH_CNTL_ZFUNC(cso->depth_func); /* maps 1:1 */
if (cso->depth.enabled)
if (cso->depth_enabled)
so->rb_depth_cntl |=
A5XX_RB_DEPTH_CNTL_Z_ENABLE |
A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
if (cso->depth.writemask)
if (cso->depth_writemask)
so->rb_depth_cntl |= A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
if (cso->stencil[0].enabled) {

8
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View File

@ -589,11 +589,11 @@ compute_ztest_mode(struct fd6_emit *emit, bool lrz_valid)
if (fs->shader->nir->info.fs.early_fragment_tests)
return A6XX_EARLY_Z;
if (fs->no_earlyz || fs->writes_pos || !zsa->base.depth.enabled ||
if (fs->no_earlyz || fs->writes_pos || !zsa->base.depth_enabled ||
fs->writes_stencilref) {
return A6XX_LATE_Z;
} else if ((fs->has_kill || zsa->alpha_test) &&
(zsa->base.depth.writemask || !pfb->zsbuf)) {
(zsa->base.depth_writemask || !pfb->zsbuf)) {
/* Slightly odd, but seems like the hw wants us to select
* LATE_Z mode if there is no depth buffer + discard. Either
* that, or when occlusion query is enabled. See:
@ -645,7 +645,7 @@ compute_lrz_state(struct fd6_emit *emit, bool binning_pass)
* we switch from GT/GE <-> LT/LE, those values cannot be
* interpreted properly.
*/
if (zsa->base.depth.enabled &&
if (zsa->base.depth_enabled &&
(rsc->lrz_direction != FD_LRZ_UNKNOWN) &&
(rsc->lrz_direction != lrz.direction)) {
rsc->lrz_valid = false;
@ -676,7 +676,7 @@ compute_lrz_state(struct fd6_emit *emit, bool binning_pass)
* of direction, it is possible to increase/decrease the z value
* to the point where the overly-conservative test is incorrect.
*/
if (zsa->base.depth.writemask) {
if (zsa->base.depth_writemask) {
rsc->lrz_direction = lrz.direction;
}

10
src/gallium/drivers/freedreno/a6xx/fd6_zsa.c
View File

@ -103,20 +103,20 @@ fd6_zsa_state_create(struct pipe_context *pctx,
so->base = *cso;
so->rb_depth_cntl |=
A6XX_RB_DEPTH_CNTL_ZFUNC(cso->depth.func); /* maps 1:1 */
A6XX_RB_DEPTH_CNTL_ZFUNC(cso->depth_func); /* maps 1:1 */
if (cso->depth.enabled) {
if (cso->depth_enabled) {
so->rb_depth_cntl |=
A6XX_RB_DEPTH_CNTL_Z_ENABLE |
A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
so->lrz.test = true;
if (cso->depth.writemask) {
if (cso->depth_writemask) {
so->lrz.write = true;
}
switch (cso->depth.func) {
switch (cso->depth_func) {
case PIPE_FUNC_LESS:
case PIPE_FUNC_LEQUAL:
so->lrz.enable = true;
@ -145,7 +145,7 @@ fd6_zsa_state_create(struct pipe_context *pctx,
}
}
if (cso->depth.writemask)
if (cso->depth_writemask)
so->rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
if (cso->stencil[0].enabled) {

4
src/gallium/drivers/freedreno/freedreno_state.h
View File

@ -32,12 +32,12 @@
static inline bool fd_depth_enabled(struct fd_context *ctx)
{
return ctx->zsa && ctx->zsa->depth.enabled;
return ctx->zsa && ctx->zsa->depth_enabled;
}
static inline bool fd_depth_write_enabled(struct fd_context *ctx)
{
return ctx->zsa && ctx->zsa->depth.writemask;
return ctx->zsa && ctx->zsa->depth_writemask;
}
static inline bool fd_stencil_enabled(struct fd_context *ctx)

6
src/gallium/drivers/i915/i915_state.c
View File

@ -525,13 +525,13 @@ i915_create_depth_stencil_state(struct pipe_context *pipe,
cso->bfo[1] = 0;
}
if (depth_stencil->depth.enabled) {
int func = i915_translate_compare_func(depth_stencil->depth.func);
if (depth_stencil->depth_enabled) {
int func = i915_translate_compare_func(depth_stencil->depth_func);
cso->depth_LIS6 |= (S6_DEPTH_TEST_ENABLE |
(func << S6_DEPTH_TEST_FUNC_SHIFT));
if (depth_stencil->depth.writemask)
if (depth_stencil->depth_writemask)
cso->depth_LIS6 |= S6_DEPTH_WRITE_ENABLE;
}

18
src/gallium/drivers/iris/iris_state.c
View File

@ -1377,14 +1377,14 @@ iris_create_zsa_state(struct pipe_context *ctx,
cso->alpha_enabled = state->alpha_enabled;
cso->alpha_func = state->alpha_func;
cso->alpha_ref_value = state->alpha_ref_value;
cso->depth_writes_enabled = state->depth.writemask;
cso->depth_test_enabled = state->depth.enabled;
cso->depth_writes_enabled = state->depth_writemask;
cso->depth_test_enabled = state->depth_enabled;
cso->stencil_writes_enabled =
state->stencil[0].writemask != 0 ||
(two_sided_stencil && state->stencil[1].writemask != 0);
/* gallium frontends need to optimize away EQUAL writes for us. */
assert(!(state->depth.func == PIPE_FUNC_EQUAL && state->depth.writemask));
assert(!(state->depth_func == PIPE_FUNC_EQUAL && state->depth_writemask));
iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), cso->wmds, wmds) {
wmds.StencilFailOp = state->stencil[0].fail_op;
@ -1397,14 +1397,14 @@ iris_create_zsa_state(struct pipe_context *ctx,
wmds.BackfaceStencilPassDepthPassOp = state->stencil[1].zpass_op;
wmds.BackfaceStencilTestFunction =
translate_compare_func(state->stencil[1].func);
wmds.DepthTestFunction = translate_compare_func(state->depth.func);
wmds.DepthTestFunction = translate_compare_func(state->depth_func);
wmds.DoubleSidedStencilEnable = two_sided_stencil;
wmds.StencilTestEnable = state->stencil[0].enabled;
wmds.StencilBufferWriteEnable =
state->stencil[0].writemask != 0 ||
(two_sided_stencil && state->stencil[1].writemask != 0);
wmds.DepthTestEnable = state->depth.enabled;
wmds.DepthBufferWriteEnable = state->depth.writemask;
wmds.DepthTestEnable = state->depth_enabled;
wmds.DepthBufferWriteEnable = state->depth_writemask;
wmds.StencilTestMask = state->stencil[0].valuemask;
wmds.StencilWriteMask = state->stencil[0].writemask;
wmds.BackfaceStencilTestMask = state->stencil[1].valuemask;
@ -1419,9 +1419,9 @@ iris_create_zsa_state(struct pipe_context *ctx,
iris_pack_command(GENX(3DSTATE_DEPTH_BOUNDS), cso->depth_bounds, depth_bounds) {
depth_bounds.DepthBoundsTestValueModifyDisable = false;
depth_bounds.DepthBoundsTestEnableModifyDisable = false;
depth_bounds.DepthBoundsTestEnable = state->depth.bounds_test;
depth_bounds.DepthBoundsTestMinValue = state->depth.bounds_min;
depth_bounds.DepthBoundsTestMaxValue = state->depth.bounds_max;
depth_bounds.DepthBoundsTestEnable = state->depth_bounds_test;
depth_bounds.DepthBoundsTestMinValue = state->depth_bounds_min;
depth_bounds.DepthBoundsTestMaxValue = state->depth_bounds_max;
}
#endif

12
src/gallium/drivers/lima/lima_draw.c
View File

@ -578,10 +578,11 @@ lima_stencil_op(enum pipe_stencil_op pipe)
}
static unsigned
lima_calculate_depth_test(struct pipe_depth_state *depth, struct pipe_rasterizer_state *rst)
lima_calculate_depth_test(struct pipe_depth_stencil_alpha_state *depth,
struct pipe_rasterizer_state *rst)
{
int offset_scale = 0, offset_units = 0;
enum pipe_compare_func func = (depth->enabled ? depth->func : PIPE_FUNC_ALWAYS);
enum pipe_compare_func func = (depth->depth_enabled ? depth->depth_func : PIPE_FUNC_ALWAYS);
offset_scale = CLAMP(rst->offset_scale * 4, -128, 127);
if (offset_scale < 0)
@ -591,7 +592,7 @@ lima_calculate_depth_test(struct pipe_depth_state *depth, struct pipe_rasterizer
if (offset_units < 0)
offset_units += 0x100;
return (depth->enabled && depth->writemask) |
return (depth->depth_enabled && depth->depth_writemask) |
((int)func << 1) |
(offset_scale << 16) |
(offset_units << 24) |
@ -639,8 +640,7 @@ lima_pack_render_state(struct lima_context *ctx, const struct pipe_draw_info *in
render->alpha_blend |= (rt->colormask & PIPE_MASK_RGBA) << 28;
struct pipe_rasterizer_state *rst = &ctx->rasterizer->base;
struct pipe_depth_state *depth = &ctx->zsa->base.depth;
render->depth_test = lima_calculate_depth_test(depth, rst);
render->depth_test = lima_calculate_depth_test(&ctx->zsa->base, rst);
ushort far, near;
@ -1010,7 +1010,7 @@ lima_draw_vbo_update(struct pipe_context *pctx,
unsigned buffers = 0;
if (fb->base.zsbuf) {
if (ctx->zsa->base.depth.enabled)
if (ctx->zsa->base.depth_enabled)
buffers |= PIPE_CLEAR_DEPTH;
if (ctx->zsa->base.stencil[0].enabled ||
ctx->zsa->base.stencil[1].enabled)

3
src/gallium/drivers/llvmpipe/lp_bld_depth.c
View File

@ -66,6 +66,7 @@
#include "gallivm/lp_bld_pack.h"
#include "lp_bld_depth.h"
#include "lp_state_fs.h"
/** Used to select fields from pipe_stencil_state */
@ -822,7 +823,7 @@ lp_build_depth_stencil_write_swizzled(struct gallivm_state *gallivm,
*/
void
lp_build_depth_stencil_test(struct gallivm_state *gallivm,
const struct pipe_depth_state *depth,
const struct lp_depth_state *depth,
const struct pipe_stencil_state stencil[2],
struct lp_type z_src_type,
const struct util_format_description *format_desc,

5
src/gallium/drivers/llvmpipe/lp_bld_depth.h
View File

@ -41,8 +41,7 @@
#include "gallivm/lp_bld.h"
struct pipe_depth_state;
struct lp_depth_state;
struct gallivm_state;
struct util_format_description;
struct lp_type;
@ -56,7 +55,7 @@ lp_depth_type(const struct util_format_description *format_desc,
void
lp_build_depth_stencil_test(struct gallivm_state *gallivm,
const struct pipe_depth_state *depth,
const struct lp_depth_state *depth,
const struct pipe_stencil_state stencil[2],
struct lp_type z_src_type,
const struct util_format_description *format_desc,

4
src/gallium/drivers/llvmpipe/lp_state_blend.c
View File

@ -115,8 +115,8 @@ llvmpipe_create_depth_stencil_state(struct pipe_context *pipe,
state = mem_dup(depth_stencil, sizeof *depth_stencil);
if (LP_PERF & PERF_NO_DEPTH) {
state->depth.enabled = 0;
state->depth.writemask = 0;
state->depth_enabled = 0;
state->depth_writemask = 0;
state->stencil[0].enabled = 0;
state->stencil[1].enabled = 0;
}

2
src/gallium/drivers/llvmpipe/lp_state_derived.c
View File

@ -229,7 +229,7 @@ void llvmpipe_update_derived( struct llvmpipe_context *llvmpipe )
(llvmpipe->sample_mask) == 0 ||
(llvmpipe->rasterizer ? llvmpipe->rasterizer->rasterizer_discard : FALSE) ||
(null_fs &&
!llvmpipe->depth_stencil->depth.enabled &&
!llvmpipe->depth_stencil->depth_enabled &&
!llvmpipe->depth_stencil->stencil[0].enabled);
lp_setup_set_rasterizer_discard(llvmpipe->setup, discard);
}

6
src/gallium/drivers/llvmpipe/lp_state_fs.c
View File

@ -3947,10 +3947,12 @@ make_variant_key(struct llvmpipe_context *lp,
const struct util_format_description *zsbuf_desc =
util_format_description(zsbuf_format);
if (lp->depth_stencil->depth.enabled &&
if (lp->depth_stencil->depth_enabled &&
util_format_has_depth(zsbuf_desc)) {
key->zsbuf_format = zsbuf_format;
memcpy(&key->depth, &lp->depth_stencil->depth, sizeof key->depth);
key->depth.enabled = lp->depth_stencil->depth_enabled;
key->depth.writemask = lp->depth_stencil->depth_writemask;
key->depth.func = lp->depth_stencil->depth_func;
}
if (lp->depth_stencil->stencil[0].enabled &&
util_format_has_stencil(zsbuf_desc)) {

10
src/gallium/drivers/llvmpipe/lp_state_fs.h
View File

@ -37,6 +37,7 @@
#include "gallivm/lp_bld_tgsi.h" /* for lp_tgsi_info */
#include "lp_bld_interp.h" /* for struct lp_shader_input */
#include "util/u_inlines.h"
#include "lp_jit.h"
struct tgsi_token;
struct lp_fragment_shader;
@ -64,9 +65,16 @@ struct lp_image_static_state
struct lp_static_texture_state image_state;
};
struct lp_depth_state
{
unsigned enabled:1; /**< depth test enabled? */
unsigned writemask:1; /**< allow depth buffer writes? */
unsigned func:3; /**< depth test func (PIPE_FUNC_x) */
};
struct lp_fragment_shader_variant_key
{
struct pipe_depth_state depth;
struct lp_depth_state depth;
struct pipe_stencil_state stencil[2];
struct pipe_blend_state blend;

12
src/gallium/drivers/nouveau/nv30/nv30_state.c
View File

@ -220,15 +220,15 @@ nv30_zsa_state_create(struct pipe_context *pipe,
so->pipe = *cso;
SB_MTHD30(so, DEPTH_FUNC, 3);
SB_DATA (so, nvgl_comparison_op(cso->depth.func));
SB_DATA (so, cso->depth.writemask);
SB_DATA (so, cso->depth.enabled);
SB_DATA (so, nvgl_comparison_op(cso->depth_func));
SB_DATA (so, cso->depth_writemask);
SB_DATA (so, cso->depth_enabled);
if (eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS) {
SB_MTHD35(so, DEPTH_BOUNDS_TEST_ENABLE, 3);
SB_DATA (so, cso->depth.bounds_test);
SB_DATA (so, fui(cso->depth.bounds_min));
SB_DATA (so, fui(cso->depth.bounds_max));
SB_DATA (so, cso->depth_bounds_test);
SB_DATA (so, fui(cso->depth_bounds_min));
SB_DATA (so, fui(cso->depth_bounds_max));
}
if (cso->stencil[0].enabled) {

12
src/gallium/drivers/nouveau/nv50/nv50_state.c
View File

@ -366,22 +366,22 @@ nv50_zsa_state_create(struct pipe_context *pipe,
so->pipe = *cso;
SB_BEGIN_3D(so, DEPTH_WRITE_ENABLE, 1);
SB_DATA (so, cso->depth.writemask);
SB_DATA (so, cso->depth_writemask);
SB_BEGIN_3D(so, DEPTH_TEST_ENABLE, 1);
if (cso->depth.enabled) {
if (cso->depth_enabled) {
SB_DATA (so, 1);
SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
SB_DATA (so, nvgl_comparison_op(cso->depth.func));
SB_DATA (so, nvgl_comparison_op(cso->depth_func));
} else {
SB_DATA (so, 0);
}
SB_BEGIN_3D(so, DEPTH_BOUNDS_EN, 1);
if (cso->depth.bounds_test) {
if (cso->depth_bounds_test) {
SB_DATA (so, 1);
SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
SB_DATA (so, fui(cso->depth.bounds_min));
SB_DATA (so, fui(cso->depth.bounds_max));
SB_DATA (so, fui(cso->depth_bounds_min));
SB_DATA (so, fui(cso->depth_bounds_max));
} else {
SB_DATA (so, 0);
}

16
src/gallium/drivers/nouveau/nvc0/nvc0_state.c
View File

@ -367,18 +367,18 @@ nvc0_zsa_state_create(struct pipe_context *pipe,
so->pipe = *cso;
SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth.enabled);
if (cso->depth.enabled) {
SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
SB_IMMED_3D(so, DEPTH_TEST_ENABLE, cso->depth_enabled);
if (cso->depth_enabled) {
SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth_writemask);
SB_BEGIN_3D(so, DEPTH_TEST_FUNC, 1);
SB_DATA (so, nvgl_comparison_op(cso->depth.func));
SB_DATA (so, nvgl_comparison_op(cso->depth_func));
}
SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth.bounds_test);
if (cso->depth.bounds_test) {
SB_IMMED_3D(so, DEPTH_BOUNDS_EN, cso->depth_bounds_test);
if (cso->depth_bounds_test) {
SB_BEGIN_3D(so, DEPTH_BOUNDS(0), 2);
SB_DATA (so, fui(cso->depth.bounds_min));
SB_DATA (so, fui(cso->depth.bounds_max));
SB_DATA (so, fui(cso->depth_bounds_min));
SB_DATA (so, fui(cso->depth_bounds_max));
}
if (cso->stencil[0].enabled) {

2
src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
View File

@ -733,7 +733,7 @@ nvc0_validate_fp_zsa_rast(struct nvc0_context *nvc0)
rasterizer_discard = true;
} else {
bool zs = nvc0->zsa &&
(nvc0->zsa->pipe.depth.enabled || nvc0->zsa->pipe.stencil[0].enabled);
(nvc0->zsa->pipe.depth_enabled || nvc0->zsa->pipe.stencil[0].enabled);
rasterizer_discard = !zs &&
(!nvc0->fragprog || !nvc0->fragprog->hdr[18]);
}

10
src/gallium/drivers/panfrost/pan_cmdstream.c
View File

@ -439,7 +439,7 @@ panfrost_prepare_midgard_fs_state(struct panfrost_context *ctx,
/* If either depth or stencil is enabled, discard matters */
bool zs_enabled =
(zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) ||
(zsa->base.depth_enabled && zsa->base.depth_func != PIPE_FUNC_ALWAYS) ||
zsa->base.stencil[0].enabled;
bool has_blend_shader = false;
@ -528,11 +528,11 @@ panfrost_prepare_fs_state(struct panfrost_context *ctx,
/* EXT_shader_framebuffer_fetch requires per-sample */
bool per_sample = ctx->min_samples > 1 || fs->outputs_read;
state->multisample_misc.evaluate_per_sample = msaa && per_sample;
state->multisample_misc.depth_function = zsa->base.depth.enabled ?
panfrost_translate_compare_func(zsa->base.depth.func) :
state->multisample_misc.depth_function = zsa->base.depth_enabled ?
panfrost_translate_compare_func(zsa->base.depth_func) :
MALI_FUNC_ALWAYS;
state->multisample_misc.depth_write_mask = zsa->base.depth.writemask;
state->multisample_misc.depth_write_mask = zsa->base.depth_writemask;
state->multisample_misc.fixed_function_near_discard = rast->depth_clip_near;
state->multisample_misc.fixed_function_far_discard = rast->depth_clip_far;
state->multisample_misc.shader_depth_range_fixed = true;
@ -623,7 +623,7 @@ panfrost_emit_frag_shader_meta(struct panfrost_batch *batch)
else
batch->draws |= PIPE_CLEAR_COLOR0;
if (ctx->depth_stencil->base.depth.enabled)
if (ctx->depth_stencil->base.depth_enabled)
batch->read |= PIPE_CLEAR_DEPTH;
if (ctx->depth_stencil->base.stencil[0].enabled)

2
src/gallium/drivers/panfrost/pan_context.c
View File

@ -1227,7 +1227,7 @@ panfrost_create_depth_stencil_state(struct pipe_context *pipe,
assert(!zsa->alpha_enabled);
/* TODO: Bounds test should be easy */
assert(!zsa->depth.bounds_test);
assert(!zsa->depth_bounds_test);
return so;
}

2
src/gallium/drivers/panfrost/pan_job.c
View File

@ -1195,7 +1195,7 @@ panfrost_batch_set_requirements(struct panfrost_batch *batch)
if (ctx->rasterizer->base.multisample)
batch->requirements |= PAN_REQ_MSAA;
if (ctx->depth_stencil && ctx->depth_stencil->base.depth.writemask) {
if (ctx->depth_stencil && ctx->depth_stencil->base.depth_writemask) {
batch->requirements |= PAN_REQ_DEPTH_WRITE;
batch->draws |= PIPE_CLEAR_DEPTH;
}

2
src/gallium/drivers/r300/r300_context.c
View File

@ -477,7 +477,7 @@ struct pipe_context* r300_create_context(struct pipe_screen* screen,
{
struct pipe_depth_stencil_alpha_state dsa;
memset(&dsa, 0, sizeof(dsa));
dsa.depth.writemask = 1;
dsa.depth_writemask = 1;
r300->dsa_decompress_zmask =
r300->context.create_depth_stencil_alpha_state(&r300->context,

24
src/gallium/drivers/r300/r300_hyperz.c
View File

@ -42,7 +42,7 @@ static enum r300_hiz_func r300_get_hiz_func(struct r300_context *r300)
{
struct r300_dsa_state *dsa = r300->dsa_state.state;
switch (dsa->dsa.depth.func) {
switch (dsa->dsa.depth_func) {
case PIPE_FUNC_NEVER:
case PIPE_FUNC_EQUAL:
case PIPE_FUNC_NOTEQUAL:
@ -63,7 +63,7 @@ static enum r300_hiz_func r300_get_hiz_func(struct r300_context *r300)
static unsigned r300_get_sc_hz_max(struct r300_context *r300)
{
struct r300_dsa_state *dsa = r300->dsa_state.state;
unsigned func = dsa->dsa.depth.func;
unsigned func = dsa->dsa.depth_func;
return func >= PIPE_FUNC_GREATER ? R300_SC_HYPERZ_MAX : R300_SC_HYPERZ_MIN;
}
@ -71,7 +71,7 @@ static unsigned r300_get_sc_hz_max(struct r300_context *r300)
static boolean r300_is_hiz_func_valid(struct r300_context *r300)
{
struct r300_dsa_state *dsa = r300->dsa_state.state;
unsigned func = dsa->dsa.depth.func;
unsigned func = dsa->dsa.depth_func;
if (r300->hiz_func == HIZ_FUNC_NONE)
return TRUE;
@ -115,13 +115,13 @@ static boolean r300_hiz_allowed(struct r300_context *r300)
r300_dsa_stencil_op_not_keep(&dsa->dsa.stencil[1]))
return FALSE;
if (dsa->dsa.depth.enabled) {
if (dsa->dsa.depth_enabled) {
/* if depth func is EQUAL pre-r500 */
if (dsa->dsa.depth.func == PIPE_FUNC_EQUAL && !r300screen->caps.is_r500)
if (dsa->dsa.depth_func == PIPE_FUNC_EQUAL && !r300screen->caps.is_r500)
return FALSE;
/* if depth func is NOTEQUAL */
if (dsa->dsa.depth.func == PIPE_FUNC_NOTEQUAL)
if (dsa->dsa.depth_func == PIPE_FUNC_NOTEQUAL)
return FALSE;
}
return TRUE;
@ -169,10 +169,10 @@ static void r300_update_hyperz(struct r300_context* r300)
}
/* Do not set anything if depth and stencil tests are off. */
if (!dsa->dsa.depth.enabled &&
if (!dsa->dsa.depth_enabled &&
!dsa->dsa.stencil[0].enabled &&
!dsa->dsa.stencil[1].enabled) {
assert(!dsa->dsa.depth.writemask);
assert(!dsa->dsa.depth_writemask);
return;
}
@ -189,12 +189,12 @@ static void r300_update_hyperz(struct r300_context* r300)
if (!r300_hiz_allowed(r300)) {
/* If writemask is disabled, the HiZ memory will not be changed,
* so we can keep its content for later. */
if (dsa->dsa.depth.writemask) {
if (dsa->dsa.depth_writemask) {
r300->hiz_in_use = FALSE;
}
return;
}
DBG(r300, DBG_HYPERZ, "r300: Z-func: %i\n", dsa->dsa.depth.func);
DBG(r300, DBG_HYPERZ, "r300: Z-func: %i\n", dsa->dsa.depth_func);
/* Set the HiZ function if needed. */
if (r300->hiz_func == HIZ_FUNC_NONE) {
@ -233,8 +233,8 @@ static boolean r300_dsa_writes_depth_stencil(
/* We are interested only in the cases when a depth or stencil value
* can be changed. */
if (dsa->depth.enabled && dsa->depth.writemask &&
dsa->depth.func != PIPE_FUNC_NEVER)
if (dsa->depth_enabled && dsa->depth_writemask &&
dsa->depth_func != PIPE_FUNC_NEVER)
return TRUE;
if (r300_dsa_writes_stencil(&dsa->stencil[0]) ||

6
src/gallium/drivers/r300/r300_state.c
View File

@ -689,15 +689,15 @@ static void* r300_create_dsa_state(struct pipe_context* pipe,
dsa->dsa = *state;
/* Depth test setup. - separate write mask depth for decomp flush */
if (state->depth.writemask) {
if (state->depth_writemask) {
z_buffer_control |= R300_Z_WRITE_ENABLE;
}
if (state->depth.enabled) {
if (state->depth_enabled) {
z_buffer_control |= R300_Z_ENABLE;
z_stencil_control |=
(r300_translate_depth_stencil_function(state->depth.func) <<
(r300_translate_depth_stencil_function(state->depth_func) <<
R300_Z_FUNC_SHIFT);
}

10
src/gallium/drivers/r600/evergreen_state.c
View File

@ -427,11 +427,11 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx,
dsa->valuemask[1] = state->stencil[1].valuemask;
dsa->writemask[0] = state->stencil[0].writemask;
dsa->writemask[1] = state->stencil[1].writemask;
dsa->zwritemask = state->depth.writemask;
dsa->zwritemask = state->depth_writemask;
db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
S_028800_ZFUNC(state->depth.func);
db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) |
S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
S_028800_ZFUNC(state->depth_func);
/* stencil */
if (state->stencil[0].enabled) {
@ -3714,7 +3714,7 @@ void *evergreen_create_fastclear_blend(struct r600_context *rctx)
void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
{
struct pipe_depth_stencil_alpha_state dsa = {{0}};
struct pipe_depth_stencil_alpha_state dsa = {{{0}}};
return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
}

12
src/gallium/drivers/r600/r600_state.c
View File

@ -415,11 +415,11 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
dsa->valuemask[1] = state->stencil[1].valuemask;
dsa->writemask[0] = state->stencil[0].writemask;
dsa->writemask[1] = state->stencil[1].writemask;
dsa->zwritemask = state->depth.writemask;
dsa->zwritemask = state->depth_writemask;
db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
S_028800_ZFUNC(state->depth.func);
db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) |
S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
S_028800_ZFUNC(state->depth_func);
/* stencil */
if (state->stencil[0].enabled) {
@ -2776,8 +2776,8 @@ void *r600_create_db_flush_dsa(struct r600_context *rctx)
memset(&dsa, 0, sizeof(dsa));
if (quirk) {
dsa.depth.enabled = 1;
dsa.depth.func = PIPE_FUNC_LEQUAL;
dsa.depth_enabled = 1;
dsa.depth_func = PIPE_FUNC_LEQUAL;
dsa.stencil[0].enabled = 1;
dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;

24
src/gallium/drivers/radeonsi/si_state.c
View File

@ -1147,8 +1147,8 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
db_depth_control =
S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
S_028800_ZFUNC(state->depth.func) | S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
S_028800_Z_ENABLE(state->depth_enabled) | S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
S_028800_ZFUNC(state->depth_func) | S_028800_DEPTH_BOUNDS_ENABLE(state->depth_bounds_test);
/* stencil */
if (state->stencil[0].enabled) {
@ -1186,13 +1186,13 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
if (state->stencil[0].enabled)
si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
if (state->depth.bounds_test) {
si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
if (state->depth_bounds_test) {
si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth_bounds_min));
si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth_bounds_max));
}
dsa->depth_enabled = state->depth.enabled;
dsa->depth_write_enabled = state->depth.enabled && state->depth.writemask;
dsa->depth_enabled = state->depth_enabled;
dsa->depth_write_enabled = state->depth_enabled && state->depth_writemask;
dsa->stencil_enabled = state->stencil[0].enabled;
dsa->stencil_write_enabled =
state->stencil[0].enabled &&
@ -1200,9 +1200,9 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
dsa->db_can_write = dsa->depth_write_enabled || dsa->stencil_write_enabled;
bool zfunc_is_ordered =
state->depth.func == PIPE_FUNC_NEVER || state->depth.func == PIPE_FUNC_LESS ||
state->depth.func == PIPE_FUNC_LEQUAL || state->depth.func == PIPE_FUNC_GREATER ||
state->depth.func == PIPE_FUNC_GEQUAL;
state->depth_func == PIPE_FUNC_NEVER || state->depth_func == PIPE_FUNC_LESS ||
state->depth_func == PIPE_FUNC_LEQUAL || state->depth_func == PIPE_FUNC_GREATER ||
state->depth_func == PIPE_FUNC_GEQUAL;
bool nozwrite_and_order_invariant_stencil =
!dsa->db_can_write ||
@ -1216,10 +1216,10 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
dsa->order_invariance[1].pass_set =
nozwrite_and_order_invariant_stencil ||
(!dsa->stencil_write_enabled &&
(state->depth.func == PIPE_FUNC_ALWAYS || state->depth.func == PIPE_FUNC_NEVER));
(state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER));
dsa->order_invariance[0].pass_set =
!dsa->depth_write_enabled ||
(state->depth.func == PIPE_FUNC_ALWAYS || state->depth.func == PIPE_FUNC_NEVER);
(state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER);
dsa->order_invariance[1].pass_last = sctx->screen->assume_no_z_fights &&
!dsa->stencil_write_enabled && dsa->depth_write_enabled &&

18
src/gallium/drivers/softpipe/sp_quad_depth_test.c
View File

@ -542,7 +542,7 @@ depth_test_quad(struct quad_stage *qs,
unsigned zmask = 0;
unsigned j;
switch (softpipe->depth_stencil->depth.func) {
switch (softpipe->depth_stencil->depth_func) {
case PIPE_FUNC_NEVER:
/* zmask = 0 */
break;
@ -600,7 +600,7 @@ depth_test_quad(struct quad_stage *qs,
* depth.writemask is FALSE, may still need to write out buffer
* data due to stencil changes.
*/
if (softpipe->depth_stencil->depth.writemask) {
if (softpipe->depth_stencil->depth_writemask) {
for (j = 0; j < TGSI_QUAD_SIZE; j++) {
if (quad->inout.mask & (1 << j)) {
data->bzzzz[j] = data->qzzzz[j];
@ -659,7 +659,7 @@ depth_stencil_test_quad(struct quad_stage *qs,
if (quad->inout.mask) {
/* now the pixels that passed the stencil test are depth tested */
if (softpipe->depth_stencil->depth.enabled) {
if (softpipe->depth_stencil->depth_enabled) {
const unsigned origMask = quad->inout.mask;
depth_test_quad(qs, data, quad); /* quad->mask is updated */
@ -794,7 +794,7 @@ depth_test_quads_fallback(struct quad_stage *qs,
}
if (qs->softpipe->framebuffer.zsbuf &&
(qs->softpipe->depth_stencil->depth.enabled ||
(qs->softpipe->depth_stencil->depth_enabled ||
qs->softpipe->depth_stencil->stencil[0].enabled)) {
float near_val, far_val;
@ -813,7 +813,7 @@ depth_test_quads_fallback(struct quad_stage *qs,
for (i = 0; i < nr; i++) {
get_depth_stencil_values(&data, quads[i]);
if (qs->softpipe->depth_stencil->depth.enabled) {
if (qs->softpipe->depth_stencil->depth_enabled) {
if (interp_depth)
interpolate_quad_depth(quads[i]);
@ -831,7 +831,7 @@ depth_test_quads_fallback(struct quad_stage *qs,
if (!depth_test_quad(qs, &data, quads[i]))
continue;
if (qs->softpipe->depth_stencil->depth.writemask)
if (qs->softpipe->depth_stencil->depth_writemask)
write_depth_stencil_values(&data, quads[i]);
}
@ -906,13 +906,13 @@ choose_depth_test(struct quad_stage *qs,
boolean alpha = qs->softpipe->depth_stencil->alpha_enabled;
boolean depth = qs->softpipe->depth_stencil->depth.enabled;
boolean depth = qs->softpipe->depth_stencil->depth_enabled;
unsigned depthfunc = qs->softpipe->depth_stencil->depth.func;
unsigned depthfunc = qs->softpipe->depth_stencil->depth_func;
boolean stencil = qs->softpipe->depth_stencil->stencil[0].enabled;
boolean depthwrite = qs->softpipe->depth_stencil->depth.writemask;
boolean depthwrite = qs->softpipe->depth_stencil->depth_writemask;
boolean occlusion = qs->softpipe->active_query_count;

2
src/gallium/drivers/softpipe/sp_quad_pipe.c
View File

@ -43,7 +43,7 @@ void
sp_build_quad_pipeline(struct softpipe_context *sp)
{
boolean early_depth_test =
(sp->depth_stencil->depth.enabled &&
(sp->depth_stencil->depth_enabled &&
sp->framebuffer.zsbuf &&
!sp->depth_stencil->alpha_enabled &&
!sp->fs_variant->info.uses_kill &&

6
src/gallium/drivers/svga/svga_pipe_depthstencil.c
View File

@ -188,10 +188,10 @@ svga_create_depth_stencil_state(struct pipe_context *pipe,
}
ds->zenable = templ->depth.enabled;
ds->zenable = templ->depth_enabled;
if (ds->zenable) {
ds->zfunc = svga_translate_compare_func(templ->depth.func);
ds->zwriteenable = templ->depth.writemask;
ds->zfunc = svga_translate_compare_func(templ->depth_func);
ds->zwriteenable = templ->depth_writemask;
}
else {
ds->zfunc = SVGA3D_CMP_ALWAYS;

2
src/gallium/drivers/svga/svga_state_rss.c
View File

@ -354,7 +354,7 @@ static struct svga_depth_stencil_state *
get_no_depth_stencil_test_state(struct svga_context *svga)
{
if (!svga->depthstencil_disable) {
struct pipe_depth_stencil_alpha_state ds = {{0}};
struct pipe_depth_stencil_alpha_state ds = {{{0}}};
svga->depthstencil_disable =
svga->pipe.create_depth_stencil_alpha_state(&svga->pipe, &ds);
}

16
src/gallium/drivers/swr/swr_state.cpp
View File

@ -1828,8 +1828,8 @@ swr_update_derived(struct pipe_context *pipe,
/* Depth/stencil state */
if (ctx->dirty & (SWR_NEW_DEPTH_STENCIL_ALPHA | SWR_NEW_FRAMEBUFFER)) {
struct pipe_depth_state *depth = &(ctx->depth_stencil->depth);
struct pipe_stencil_state *stencil = ctx->depth_stencil->stencil;
struct pipe_depth_stencil_alpha_state *depth = ctx->depth_stencil;
struct pipe_stencil_state *stencil = depth->stencil;
SWR_DEPTH_STENCIL_STATE depthStencilState = {{0}};
SWR_DEPTH_BOUNDS_STATE depthBoundsState = {0};
@ -1873,14 +1873,14 @@ swr_update_derived(struct pipe_context *pipe,
ctx->stencil_ref.ref_value[1];
}
depthStencilState.depthTestEnable = depth->enabled;
depthStencilState.depthTestFunc = swr_convert_depth_func(depth->func);
depthStencilState.depthWriteEnable = depth->writemask;
depthStencilState.depthTestEnable = depth->depth_enabled;
depthStencilState.depthTestFunc = swr_convert_depth_func(depth->depth_func);
depthStencilState.depthWriteEnable = depth->depth_writemask;
ctx->api.pfnSwrSetDepthStencilState(ctx->swrContext, &depthStencilState);
depthBoundsState.depthBoundsTestEnable = depth->bounds_test;
depthBoundsState.depthBoundsTestMinValue = depth->bounds_min;
depthBoundsState.depthBoundsTestMaxValue = depth->bounds_max;
depthBoundsState.depthBoundsTestEnable = depth->depth_bounds_test;
depthBoundsState.depthBoundsTestMinValue = depth->depth_bounds_min;
depthBoundsState.depthBoundsTestMaxValue = depth->depth_bounds_max;
ctx->api.pfnSwrSetDepthBoundsState(ctx->swrContext, &depthBoundsState);
}

4
src/gallium/drivers/v3d/v3dx_draw.c
View File

@ -1399,12 +1399,12 @@ v3d_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
for (int i = 0; i < v3d->streamout.num_targets; i++)
v3d->streamout.offsets[i] += draws[0].count;
if (v3d->zsa && job->zsbuf && v3d->zsa->base.depth.enabled) {
if (v3d->zsa && job->zsbuf && v3d->zsa->base.depth_enabled) {
struct v3d_resource *rsc = v3d_resource(job->zsbuf->texture);
v3d_job_add_bo(job, rsc->bo);
job->load |= PIPE_CLEAR_DEPTH & ~job->clear;
if (v3d->zsa->base.depth.writemask)
if (v3d->zsa->base.depth_writemask)
job->store |= PIPE_CLEAR_DEPTH;
rsc->initialized_buffers = PIPE_CLEAR_DEPTH;
}

6
src/gallium/drivers/v3d/v3dx_emit.c
View File

@ -514,13 +514,13 @@ v3dX(emit_state)(struct pipe_context *pctx)
*/
config.early_z_updates_enable =
(job->ez_state != VC5_EZ_DISABLED);
if (v3d->zsa->base.depth.enabled) {
if (v3d->zsa->base.depth_enabled) {
config.z_updates_enable =
v3d->zsa->base.depth.writemask;
v3d->zsa->base.depth_writemask;
config.early_z_enable =
config.early_z_updates_enable;
config.depth_test_function =
v3d->zsa->base.depth.func;
v3d->zsa->base.depth_func;
} else {
config.depth_test_function = PIPE_FUNC_ALWAYS;
}

4
src/gallium/drivers/v3d/v3dx_state.c
View File

@ -175,8 +175,8 @@ v3d_create_depth_stencil_alpha_state(struct pipe_context *pctx,
so->base = *cso;
if (cso->depth.enabled) {
switch (cso->depth.func) {
if (cso->depth_enabled) {
switch (cso->depth_func) {
case PIPE_FUNC_LESS:
case PIPE_FUNC_LEQUAL:
so->ez_state = VC5_EZ_LT_LE;

2
src/gallium/drivers/vc4/vc4_draw.c
View File

@ -484,7 +484,7 @@ vc4_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info,
struct vc4_resource *rsc =
vc4_resource(vc4->framebuffer.zsbuf->texture);
if (vc4->zsa->base.depth.enabled) {
if (vc4->zsa->base.depth_enabled) {
job->resolve |= PIPE_CLEAR_DEPTH;
rsc->initialized_buffers = PIPE_CLEAR_DEPTH;
}

2
src/gallium/drivers/vc4/vc4_program.c
View File

@ -2737,7 +2737,7 @@ vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
key->depth_enabled = (vc4->zsa->base.depth.enabled ||
key->depth_enabled = (vc4->zsa->base.depth_enabled ||
key->stencil_enabled);
if (vc4->zsa->base.alpha_enabled)
key->alpha_test_func = vc4->zsa->base.alpha_func;

10
src/gallium/drivers/vc4/vc4_state.c
View File

@ -220,19 +220,19 @@ vc4_create_depth_stencil_alpha_state(struct pipe_context *pctx,
*/
so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE;
if (cso->depth.enabled) {
if (cso->depth.writemask) {
if (cso->depth_enabled) {
if (cso->depth_writemask) {
so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE;
}
so->config_bits[1] |= (cso->depth.func <<
so->config_bits[1] |= (cso->depth_func <<
VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
/* We only handle early Z in the < direction because otherwise
* we'd have to runtime guess which direction to set in the
* render config.
*/
if ((cso->depth.func == PIPE_FUNC_LESS ||
cso->depth.func == PIPE_FUNC_LEQUAL) &&
if ((cso->depth_func == PIPE_FUNC_LESS ||
cso->depth_func == PIPE_FUNC_LEQUAL) &&
(!cso->stencil[0].enabled ||
(cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP &&
(!cso->stencil[1].enabled ||

6
src/gallium/drivers/virgl/virgl_encode.c
View File

@ -367,9 +367,9 @@ int virgl_encode_dsa_state(struct virgl_context *ctx,
virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_CREATE_OBJECT, VIRGL_OBJECT_DSA, VIRGL_OBJ_DSA_SIZE));
virgl_encoder_write_dword(ctx->cbuf, handle);
tmp = VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(dsa_state->depth.enabled) |
VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) |
VIRGL_OBJ_DSA_S0_DEPTH_FUNC(dsa_state->depth.func) |
tmp = VIRGL_OBJ_DSA_S0_DEPTH_ENABLE(dsa_state->depth_enabled) |
VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth_writemask) |
VIRGL_OBJ_DSA_S0_DEPTH_FUNC(dsa_state->depth_func) |
VIRGL_OBJ_DSA_S0_ALPHA_ENABLED(dsa_state->alpha_enabled) |
VIRGL_OBJ_DSA_S0_ALPHA_FUNC(dsa_state->alpha_func);
virgl_encoder_write_dword(ctx->cbuf, tmp);

12
src/gallium/drivers/zink/zink_state.c
View File

@ -336,15 +336,15 @@ zink_create_depth_stencil_alpha_state(struct pipe_context *pctx,
cso->base = *depth_stencil_alpha;
if (depth_stencil_alpha->depth.enabled) {
if (depth_stencil_alpha->depth_enabled) {
cso->hw_state.depth_test = VK_TRUE;
cso->hw_state.depth_compare_op = compare_op(depth_stencil_alpha->depth.func);
cso->hw_state.depth_compare_op = compare_op(depth_stencil_alpha->depth_func);
}
if (depth_stencil_alpha->depth.bounds_test) {
if (depth_stencil_alpha->depth_bounds_test) {
cso->hw_state.depth_bounds_test = VK_TRUE;
cso->hw_state.min_depth_bounds = depth_stencil_alpha->depth.bounds_min;
cso->hw_state.max_depth_bounds = depth_stencil_alpha->depth.bounds_max;
cso->hw_state.min_depth_bounds = depth_stencil_alpha->depth_bounds_min;
cso->hw_state.max_depth_bounds = depth_stencil_alpha->depth_bounds_max;
}
if (depth_stencil_alpha->stencil[0].enabled) {
@ -357,7 +357,7 @@ zink_create_depth_stencil_alpha_state(struct pipe_context *pctx,
else
cso->hw_state.stencil_back = cso->hw_state.stencil_front;
cso->hw_state.depth_write = depth_stencil_alpha->depth.writemask;
cso->hw_state.depth_write = depth_stencil_alpha->depth_writemask;
return cso;
}

16
src/gallium/frontends/lavapipe/lvp_execute.c
View File

@ -479,14 +479,14 @@ static void handle_graphics_pipeline(struct lvp_cmd_buffer_entry *cmd,
if (pipeline->graphics_create_info.pDepthStencilState) {
const VkPipelineDepthStencilStateCreateInfo *dsa = pipeline->graphics_create_info.pDepthStencilState;
state->dsa_state.depth.enabled = dsa->depthTestEnable;
state->dsa_state.depth.writemask = dsa->depthWriteEnable;
state->dsa_state.depth.func = dsa->depthCompareOp;
state->dsa_state.depth.bounds_test = dsa->depthBoundsTestEnable;
state->dsa_state.depth_enabled = dsa->depthTestEnable;
state->dsa_state.depth_writemask = dsa->depthWriteEnable;
state->dsa_state.depth_func = dsa->depthCompareOp;
state->dsa_state.depth_bounds_test = dsa->depthBoundsTestEnable;
if (!dynamic_states[VK_DYNAMIC_STATE_DEPTH_BOUNDS]) {
state->dsa_state.depth.bounds_min = dsa->minDepthBounds;
state->dsa_state.depth.bounds_max = dsa->maxDepthBounds;
state->dsa_state.depth_bounds_min = dsa->minDepthBounds;
state->dsa_state.depth_bounds_max = dsa->maxDepthBounds;
}
state->dsa_state.stencil[0].enabled = dsa->stencilTestEnable;
@ -1402,8 +1402,8 @@ static void handle_set_blend_constants(struct lvp_cmd_buffer_entry *cmd,
static void handle_set_depth_bounds(struct lvp_cmd_buffer_entry *cmd,
struct rendering_state *state)
{
state->dsa_state.depth.bounds_min = cmd->u.set_depth_bounds.min_depth;
state->dsa_state.depth.bounds_max = cmd->u.set_depth_bounds.max_depth;
state->dsa_state.depth_bounds_min = cmd->u.set_depth_bounds.min_depth;
state->dsa_state.depth_bounds_max = cmd->u.set_depth_bounds.max_depth;
state->dsa_dirty = true;
}

10
src/gallium/frontends/nine/nine_pipe.c
View File

@ -35,12 +35,12 @@ nine_convert_dsa_state(struct pipe_depth_stencil_alpha_state *dsa_state,
memset(&dsa, 0, sizeof(dsa)); /* memcmp safety */
if (rs[D3DRS_ZENABLE]) {
dsa.depth.enabled = 1;
dsa.depth.func = d3dcmpfunc_to_pipe_func(rs[D3DRS_ZFUNC]);
dsa.depth_enabled = 1;
dsa.depth_func = d3dcmpfunc_to_pipe_func(rs[D3DRS_ZFUNC]);
/* Disable depth write if no change can occur */
dsa.depth.writemask = !!rs[D3DRS_ZWRITEENABLE] &&
dsa.depth.func != PIPE_FUNC_EQUAL &&
dsa.depth.func != PIPE_FUNC_NEVER;
dsa.depth_writemask = !!rs[D3DRS_ZWRITEENABLE] &&
dsa.depth_func != PIPE_FUNC_EQUAL &&
dsa.depth_func != PIPE_FUNC_NEVER;
}
if (rs[D3DRS_STENCILENABLE]) {

25
src/gallium/include/pipe/p_state.h
View File

@ -301,16 +301,6 @@ pipe_shader_state_from_tgsi(struct pipe_shader_state *state,
memset(&state->stream_output, 0, sizeof(state->stream_output));
}
struct pipe_depth_state
{
unsigned enabled:1; /**< depth test enabled? */
unsigned writemask:1; /**< allow depth buffer writes? */
unsigned func:3; /**< depth test func (PIPE_FUNC_x) */
unsigned bounds_test:1; /**< depth bounds test enabled? */
float bounds_min; /**< minimum depth bound */
float bounds_max; /**< maximum depth bound */
};
struct pipe_stencil_state
{
@ -326,12 +316,19 @@ struct pipe_stencil_state
struct pipe_depth_stencil_alpha_state
{
struct pipe_depth_state depth;
struct pipe_stencil_state stencil[2]; /**< [0] = front, [1] = back */
unsigned alpha_enabled:1; /**< alpha test enabled? */
unsigned alpha_func:3; /**< PIPE_FUNC_x */
float alpha_ref_value; /**< reference value */
unsigned alpha_enabled:1; /**< alpha test enabled? */
unsigned alpha_func:3; /**< PIPE_FUNC_x */
unsigned depth_enabled:1; /**< depth test enabled? */
unsigned depth_writemask:1; /**< allow depth buffer writes? */
unsigned depth_func:3; /**< depth test func (PIPE_FUNC_x) */
unsigned depth_bounds_test:1; /**< depth bounds test enabled? */
float alpha_ref_value; /**< reference value */
float depth_bounds_min; /**< minimum depth bound */
float depth_bounds_max; /**< maximum depth bound */
};

6
src/gallium/tests/graw/graw_util.h
View File

@ -160,9 +160,9 @@ graw_util_default_state(struct graw_info *info, boolean depth_test)
struct pipe_depth_stencil_alpha_state depthStencilAlpha;
void *handle;
memset(&depthStencilAlpha, 0, sizeof depthStencilAlpha);
depthStencilAlpha.depth.enabled = depth_test;
depthStencilAlpha.depth.writemask = 1;
depthStencilAlpha.depth.func = PIPE_FUNC_LESS;
depthStencilAlpha.depth_enabled = depth_test;
depthStencilAlpha.depth_writemask = 1;
depthStencilAlpha.depth_func = PIPE_FUNC_LESS;
handle = info->ctx->create_depth_stencil_alpha_state(info->ctx,
&depthStencilAlpha);
info->ctx->bind_depth_stencil_alpha_state(info->ctx, handle);

14
src/mesa/state_tracker/st_atom_depth.c
View File

@ -106,15 +106,15 @@ st_update_depth_stencil_alpha(struct st_context *st)
if (ctx->DrawBuffer->Visual.depthBits > 0) {
if (ctx->Depth.Test) {
dsa->depth.enabled = 1;
dsa->depth.func = st_compare_func_to_pipe(ctx->Depth.Func);
if (dsa->depth.func != PIPE_FUNC_EQUAL)
dsa->depth.writemask = ctx->Depth.Mask;
dsa->depth_enabled = 1;
dsa->depth_func = st_compare_func_to_pipe(ctx->Depth.Func);
if (dsa->depth_func != PIPE_FUNC_EQUAL)
dsa->depth_writemask = ctx->Depth.Mask;
}
if (ctx->Depth.BoundsTest) {
dsa->depth.bounds_test = 1;
dsa->depth.bounds_min = ctx->Depth.BoundsMin;
dsa->depth.bounds_max = ctx->Depth.BoundsMax;
dsa->depth_bounds_test = 1;
dsa->depth_bounds_min = ctx->Depth.BoundsMin;
dsa->depth_bounds_max = ctx->Depth.BoundsMax;
}
}

6
src/mesa/state_tracker/st_cb_clear.c
View File

@ -300,9 +300,9 @@ clear_with_quad(struct gl_context *ctx, unsigned clear_buffers)
struct pipe_depth_stencil_alpha_state depth_stencil;
memset(&depth_stencil, 0, sizeof(depth_stencil));
if (clear_buffers & PIPE_CLEAR_DEPTH) {
depth_stencil.depth.enabled = 1;
depth_stencil.depth.writemask = 1;
depth_stencil.depth.func = PIPE_FUNC_ALWAYS;
depth_stencil.depth_enabled = 1;
depth_stencil.depth_writemask = 1;
depth_stencil.depth_func = PIPE_FUNC_ALWAYS;
}
if (clear_buffers & PIPE_CLEAR_STENCIL) {

6
src/mesa/state_tracker/st_cb_drawpixels.c
View File

@ -809,9 +809,9 @@ draw_textured_quad(struct gl_context *ctx, GLint x, GLint y, GLfloat z,
dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_REPLACE;
if (write_depth) {
/* writing depth+stencil: depth test always passes */
dsa.depth.enabled = 1;
dsa.depth.writemask = ctx->Depth.Mask;
dsa.depth.func = PIPE_FUNC_ALWAYS;
dsa.depth_enabled = 1;
dsa.depth_writemask = ctx->Depth.Mask;
dsa.depth_func = PIPE_FUNC_ALWAYS;
}
cso_set_depth_stencil_alpha(cso, &dsa);