pan/midgard: Implement class spilling
We reuse the same register spilling mechanism as for work->memory to spill special->work registers, e.g. to allow writing out more than 2 vec4 varyings (without better scheduling anyway). Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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@ -707,26 +707,40 @@ schedule_program(compiler_context *ctx)
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assert(0);
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}
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/* Allocate TLS slot */
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unsigned spill_slot = spill_count++;
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/* Check the class. Work registers legitimately spill
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* to TLS, but special registers just spill to work
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* registers */
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unsigned class = ra_get_node_class(g, spill_node);
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bool is_special = (class >> 2) != REG_CLASS_WORK;
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/* Replace all stores to the spilled node with stores
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* to TLS */
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/* Allocate TLS slot (maybe) */
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unsigned spill_slot = !is_special ? spill_count++ : 0;
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mir_foreach_instr_global_safe(ctx, ins) {
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if (ins->compact_branch) continue;
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if (ins->ssa_args.dest != spill_node) continue;
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ins->ssa_args.dest = SSA_FIXED_REGISTER(26);
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/* For TLS, replace all stores to the spilled node. For
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* special, just keep as-is; the class will be demoted
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* implicitly */
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midgard_instruction st = v_load_store_scratch(ins->ssa_args.dest, spill_slot, true, ins->mask);
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mir_insert_instruction_before(mir_next_op(ins), st);
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if (!is_special) {
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mir_foreach_instr_global_safe(ctx, ins) {
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if (ins->compact_branch) continue;
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if (ins->ssa_args.dest != spill_node) continue;
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ins->ssa_args.dest = SSA_FIXED_REGISTER(26);
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ctx->spills++;
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midgard_instruction st = v_load_store_scratch(ins->ssa_args.dest, spill_slot, true, ins->mask);
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mir_insert_instruction_before(mir_next_op(ins), st);
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ctx->spills++;
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}
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}
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/* Insert a load from TLS before the first consecutive
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* use of the node, rewriting to use spilled indices to
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* break up the live range */
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* break up the live range. Or, for special, insert a
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* move. Ironically the latter *increases* register
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* pressure, but the two uses of the spilling mechanism
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* are somewhat orthogonal. (special spilling is to use
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* work registers to back special registers; TLS
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* spilling is to use memory to back work registers) */
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mir_foreach_block(ctx, block) {
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@ -748,13 +762,23 @@ schedule_program(compiler_context *ctx)
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}
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consecutive_index = ++spill_index;
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midgard_instruction st = v_load_store_scratch(consecutive_index, spill_slot, false, 0xF);
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midgard_instruction *before = ins;
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/* For a csel, go back one more not to break up the bundle */
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if (ins->type == TAG_ALU_4 && OP_IS_CSEL(ins->alu.op))
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before = mir_prev_op(before);
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midgard_instruction st;
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if (is_special) {
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/* Move */
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st = v_mov(spill_node, blank_alu_src, consecutive_index);
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} else {
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/* TLS load */
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st = v_load_store_scratch(consecutive_index, spill_slot, false, 0xF);
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}
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mir_insert_instruction_before(before, st);
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// consecutive_skip = true;
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@ -762,7 +786,8 @@ schedule_program(compiler_context *ctx)
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/* Rewrite to use */
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mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
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ctx->fills++;
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if (!is_special)
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ctx->fills++;
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}
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}
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}
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