i965/compaction: Use sizeof brw_inst/brw_compact_inst.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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@ -1098,11 +1098,11 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
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/* For an instruction at byte offset 8*i before compaction, this is the number
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* of compacted instructions that preceded it.
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*/
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int compacted_counts[(p->next_insn_offset - start_offset) / 8];
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int compacted_counts[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst)];
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/* For an instruction at byte offset 8*i after compaction, this is the
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* 8-byte offset it was at before compaction.
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*/
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int old_ip[(p->next_insn_offset - start_offset) / 8];
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int old_ip[(p->next_insn_offset - start_offset) / sizeof(brw_compact_inst)];
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if (brw->gen < 6)
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return;
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@ -1114,8 +1114,8 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
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brw_inst *src = store + src_offset;
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void *dst = store + offset;
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old_ip[offset / 8] = src_offset / 8;
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compacted_counts[src_offset / 8] = compacted_count;
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old_ip[offset / sizeof(brw_compact_inst)] = src_offset / sizeof(brw_compact_inst);
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compacted_counts[src_offset / sizeof(brw_compact_inst)] = compacted_count;
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brw_inst saved = *src;
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@ -1130,7 +1130,7 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
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}
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}
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offset += 8;
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offset += sizeof(brw_compact_inst);
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} else {
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/* It appears that the end of thread SEND instruction needs to be
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* aligned, or the GPU hangs.
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@ -1138,13 +1138,14 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
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if ((brw_inst_opcode(brw, src) == BRW_OPCODE_SEND ||
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brw_inst_opcode(brw, src) == BRW_OPCODE_SENDC) &&
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brw_inst_eot(brw, src) &&
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(offset & 8) != 0) {
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(offset & sizeof(brw_compact_inst)) != 0) {
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brw_compact_inst *align = store + offset;
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memset(align, 0, sizeof(*align));
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brw_compact_inst_set_opcode(align, BRW_OPCODE_NOP);
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brw_compact_inst_set_cmpt_control(align, true);
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offset += 8;
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old_ip[offset / 8] = src_offset / 8;
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offset += sizeof(brw_compact_inst);
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old_ip[offset / sizeof(brw_compact_inst)] = src_offset / sizeof(brw_compact_inst);
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dst = store + offset;
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}
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@ -1163,7 +1164,7 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
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for (offset = 0; offset < p->next_insn_offset - start_offset;
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offset = next_offset(brw, store, offset)) {
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brw_inst *insn = store + offset;
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int this_old_ip = old_ip[offset / 8];
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int this_old_ip = old_ip[offset / sizeof(brw_compact_inst)];
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int this_compacted_count = compacted_counts[this_old_ip];
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int target_old_ip, target_compacted_count;
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@ -1196,21 +1197,22 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
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* alignment padding, so that the next compression pass (for the FS 8/16
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* compile passes) parses correctly.
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*/
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if (p->next_insn_offset & 8) {
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if (p->next_insn_offset & sizeof(brw_compact_inst)) {
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brw_compact_inst *align = store + offset;
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memset(align, 0, sizeof(*align));
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brw_compact_inst_set_opcode(align, BRW_OPCODE_NOP);
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brw_compact_inst_set_cmpt_control(align, true);
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p->next_insn_offset += 8;
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p->next_insn_offset += sizeof(brw_compact_inst);
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}
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p->nr_insn = p->next_insn_offset / 16;
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p->nr_insn = p->next_insn_offset / sizeof(brw_inst);
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/* Update the instruction offsets for each annotation. */
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if (annotation) {
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for (int offset = 0, i = 0; i < num_annotations; i++) {
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while (start_offset + old_ip[offset / 8] * 8 != annotation[i].offset) {
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assert(start_offset + old_ip[offset / 8] * 8 <
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annotation[i].offset);
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while (start_offset + old_ip[offset / sizeof(brw_compact_inst)] *
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sizeof(brw_compact_inst) != annotation[i].offset) {
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assert(start_offset + old_ip[offset / sizeof(brw_compact_inst)] *
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sizeof(brw_compact_inst) < annotation[i].offset);
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offset = next_offset(brw, store, offset);
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}
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