i965: Update workaround flush comments for Gen6 3DSTATE_VS.

Unfortunately, the workaround text never made it into the Sandybridge
PRM, so we still have to refer to the BSpec.

It also wasn't obvious why we needed this workaround at all, since we
don't currently do VS passthrough - but BLORP can turn off the VS.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

src/mesa/drivers/dri/i965/gen6_blorp.cpp

@@ -554,7 +554,7 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw,
                            const brw_blorp_params *params)
 {
    if (brw->gen == 6) {
-      /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
+      /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
        * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
        *
        *   [DevSNB] A pipeline flush must be programmed prior to a

src/mesa/drivers/dri/i965/gen6_vs_state.c

@@ -101,12 +101,16 @@ upload_vs_state(struct brw_context *brw)
    struct gl_context *ctx = &brw->ctx;
    uint32_t floating_point_mode = 0;
 
-   /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section
+   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
     * 3DSTATE_VS, Dword 5.0 "VS Function Enable":
+    *
     *   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
     *   command that causes the VS Function Enable to toggle. Pipeline
     *   flush can be executed by sending a PIPE_CONTROL command with CS
     *   stall bit set and a post sync operation.
+    *
+    * Although we don't disable the VS during normal drawing, BLORP sometimes
+    * disables it.  To be safe, do the flush here just in case.
     */
    intel_emit_post_sync_nonzero_flush(brw);