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r600: add support for ARB_shader_clock. 

Reviewed-by: Gert Wollny <gw.fossedev@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie 2017-11-21 07:29:09 +10:00
parent 6785034a70
commit 9041730d1c
4 changed files with 30 additions and 6 deletions
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2
docs/features.txt
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@ -305,7 +305,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve
GL_ARB_sample_locations not started
GL_ARB_seamless_cubemap_per_texture DONE (i965, nvc0, radeonsi, r600, softpipe, swr)
GL_ARB_shader_ballot DONE (i965/gen8+, nvc0, radeonsi)
GL_ARB_shader_clock DONE (i965/gen7+, nv50, nvc0, radeonsi)
GL_ARB_shader_clock DONE (i965/gen7+, nv50, nvc0, r600, radeonsi)
GL_ARB_shader_stencil_export DONE (i965/gen9+, r600, radeonsi, softpipe, llvmpipe, swr)
GL_ARB_shader_viewport_layer_array DONE (i965/gen6+, nvc0, radeonsi)
GL_ARB_sparse_buffer DONE (radeonsi/CIK+)

2
src/gallium/drivers/r600/r600_pipe.c
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@ -350,6 +350,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
case PIPE_CAP_TGSI_CLOCK:
return family >= CHIP_CEDAR ? 1 : 0;
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return family >= CHIP_CEDAR ? 4 : 0;
@ -394,7 +395,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
case PIPE_CAP_TGSI_TEX_TXF_LZ:
case PIPE_CAP_TGSI_CLOCK:
case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
case PIPE_CAP_TGSI_BALLOT:

29
src/gallium/drivers/r600/r600_shader.c
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@ -10190,6 +10190,29 @@ static int tgsi_bfe(struct r600_shader_ctx *ctx)
return 0;
}
static int tgsi_clock(struct r600_shader_ctx *ctx)
{
struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
struct r600_bytecode_alu alu;
int r;
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP1_MOV;
tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_LO;
r = r600_bytecode_add_alu(ctx->bc, &alu);
if (r)
return r;
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP1_MOV;
tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
r = r600_bytecode_add_alu(ctx->bc, &alu);
if (r)
return r;
return 0;
}
static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[] = {
[TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
[TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
@ -10226,7 +10249,7 @@ static const struct r600_shader_tgsi_instruction r600_shader_tgsi_instruction[]
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
[31] = { ALU_OP0_NOP, tgsi_unsupported},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
[33] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_unsupported},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[35] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
@ -10424,7 +10447,7 @@ static const struct r600_shader_tgsi_instruction eg_shader_tgsi_instruction[] =
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
[31] = { ALU_OP0_NOP, tgsi_unsupported},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
[33] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[35] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
@ -10646,7 +10669,7 @@ static const struct r600_shader_tgsi_instruction cm_shader_tgsi_instruction[] =
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, cayman_pow},
[31] = { ALU_OP0_NOP, tgsi_unsupported},
[32] = { ALU_OP0_NOP, tgsi_unsupported},
[33] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
[34] = { ALU_OP0_NOP, tgsi_unsupported},
[35] = { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_COS] = { ALU_OP1_COS, cayman_trig},

3
src/gallium/drivers/r600/r600_sq.h
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@ -196,7 +196,8 @@
#define EG_V_SQ_ALU_SRC_LDS_OQ_B_POP 0x000000DE
#define EG_V_SQ_ALU_SRC_LDS_DIRECT_A 0x000000DF
#define EG_V_SQ_ALU_SRC_LDS_DIRECT_B 0x000000E0
#define EG_V_SQ_ALU_SRC_TIME_HI 0x000000E3
#define EG_V_SQ_ALU_SRC_TIME_LO 0x000000E4
#define EG_V_SQ_ALU_SRC_HW_WAVE_ID 0x000000E7
#define EG_V_SQ_ALU_SRC_SIMD_ID 0x000000E8
#define EG_V_SQ_ALU_SRC_SE_ID 0x000000E9