KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

radv: use updated tokens from vk.xml 

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17342>
This commit is contained in:
Eric Engestrom 2022-07-01 13:03:58 +01:00 committed by Marge Bot
parent 9844a2fb64
commit 9035408d62
11 changed files with 45 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/amd/vulkan/radv_android.c
View File

@ -582,13 +582,13 @@ get_ahb_buffer_format_properties2(VkDevice device_h, const struct AHardwareBuffe
* the Android hardware buffer’s format has a Vulkan equivalent."
*
* "The formatFeatures member *must* include
* VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT_KHR and at least one of
* VK_FORMAT_FEATURE_2_MIDPOINT_CHROMA_SAMPLES_BIT_KHR or
* VK_FORMAT_FEATURE_2_COSITED_CHROMA_SAMPLES_BIT_KHR"
* VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT and at least one of
* VK_FORMAT_FEATURE_2_MIDPOINT_CHROMA_SAMPLES_BIT or
* VK_FORMAT_FEATURE_2_COSITED_CHROMA_SAMPLES_BIT"
*/
assert(p->formatFeatures & VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT_KHR);
assert(p->formatFeatures & VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT);
p->formatFeatures |= VK_FORMAT_FEATURE_2_MIDPOINT_CHROMA_SAMPLES_BIT_KHR;
p->formatFeatures |= VK_FORMAT_FEATURE_2_MIDPOINT_CHROMA_SAMPLES_BIT;
/* "Implementations may not always be able to determine the color model,
* numerical range, or chroma offsets of the image contents, so the values

8
src/amd/vulkan/radv_cmd_buffer.c
View File

@ -3950,11 +3950,11 @@ radv_stage_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_s
VK_PIPELINE_STAGE_2_BLIT_BIT |
VK_PIPELINE_STAGE_2_CLEAR_BIT)) {
/* Be conservative for now. */
src_stage_mask |= VK_PIPELINE_STAGE_2_TRANSFER_BIT;
src_stage_mask |= VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT;
}
if (src_stage_mask &
(VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT | VK_PIPELINE_STAGE_2_TRANSFER_BIT |
(VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT | VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT |
VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR |
VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR |
VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT |
@ -3965,7 +3965,7 @@ radv_stage_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_s
if (src_stage_mask &
(VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT | VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT |
VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT |
VK_PIPELINE_STAGE_2_TRANSFER_BIT | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT |
VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT |
VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)) {
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
} else if (src_stage_mask &
@ -8726,7 +8726,7 @@ write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event,
VK_PIPELINE_STAGE_2_BLIT_BIT |
VK_PIPELINE_STAGE_2_CLEAR_BIT)) {
/* Be conservative for now. */
stageMask |= VK_PIPELINE_STAGE_2_TRANSFER_BIT;
stageMask |= VK_PIPELINE_STAGE_2_ALL_TRANSFER_BIT;
}
/* Flags that only require a top-of-pipe event. */

4
src/amd/vulkan/radv_descriptor_set.c
View File

@ -291,7 +291,7 @@ radv_CreateDescriptorSetLayout(VkDevice _device, const VkDescriptorSetLayoutCrea
if (variable_flags && binding->binding < variable_flags->bindingCount &&
(variable_flags->pBindingFlags[binding->binding] &
VK_DESCRIPTOR_BINDING_VARIABLE_DESCRIPTOR_COUNT_BIT_EXT)) {
VK_DESCRIPTOR_BINDING_VARIABLE_DESCRIPTOR_COUNT_BIT)) {
assert(
!binding->pImmutableSamplers); /* Terribly ill defined how many samplers are valid */
assert(binding->binding == num_bindings - 1);
@ -465,7 +465,7 @@ radv_GetDescriptorSetLayoutSupport(VkDevice device,
}
if (variable_flags && binding->binding < variable_flags->bindingCount && variable_count &&
(variable_flags->pBindingFlags[binding->binding] &
VK_DESCRIPTOR_BINDING_VARIABLE_DESCRIPTOR_COUNT_BIT_EXT)) {
VK_DESCRIPTOR_BINDING_VARIABLE_DESCRIPTOR_COUNT_BIT)) {
variable_count->maxVariableDescriptorCount = MIN2(UINT32_MAX, max_count);
}
size += descriptor_count * descriptor_size;

52
src/amd/vulkan/radv_device.c
View File

@ -1634,9 +1634,9 @@ radv_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice,
features->extendedDynamicState2PatchControlPoints = false;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_GLOBAL_PRIORITY_QUERY_FEATURES_EXT: {
VkPhysicalDeviceGlobalPriorityQueryFeaturesEXT *features =
(VkPhysicalDeviceGlobalPriorityQueryFeaturesEXT *)ext;
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_GLOBAL_PRIORITY_QUERY_FEATURES_KHR: {
VkPhysicalDeviceGlobalPriorityQueryFeaturesKHR *features =
(VkPhysicalDeviceGlobalPriorityQueryFeaturesKHR *)ext;
features->globalPriorityQuery = true;
break;
}
@ -2572,11 +2572,11 @@ radv_get_physical_device_queue_family_properties(struct radv_physical_device *pd
*pCount = idx;
}
static const VkQueueGlobalPriorityEXT radv_global_queue_priorities[] = {
VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT,
VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT,
VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT,
VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT,
static const VkQueueGlobalPriorityKHR radv_global_queue_priorities[] = {
VK_QUEUE_GLOBAL_PRIORITY_LOW_KHR,
VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_KHR,
VK_QUEUE_GLOBAL_PRIORITY_HIGH_KHR,
VK_QUEUE_GLOBAL_PRIORITY_REALTIME_KHR,
};
VKAPI_ATTR void VKAPI_CALL
@ -2600,10 +2600,10 @@ radv_GetPhysicalDeviceQueueFamilyProperties2(VkPhysicalDevice physicalDevice, ui
vk_foreach_struct(ext, pQueueFamilyProperties[i].pNext)
{
switch (ext->sType) {
case VK_STRUCTURE_TYPE_QUEUE_FAMILY_GLOBAL_PRIORITY_PROPERTIES_EXT: {
VkQueueFamilyGlobalPriorityPropertiesEXT *prop =
(VkQueueFamilyGlobalPriorityPropertiesEXT *)ext;
STATIC_ASSERT(ARRAY_SIZE(radv_global_queue_priorities) <= VK_MAX_GLOBAL_PRIORITY_SIZE_EXT);
case VK_STRUCTURE_TYPE_QUEUE_FAMILY_GLOBAL_PRIORITY_PROPERTIES_KHR: {
VkQueueFamilyGlobalPriorityPropertiesKHR *prop =
(VkQueueFamilyGlobalPriorityPropertiesKHR *)ext;
STATIC_ASSERT(ARRAY_SIZE(radv_global_queue_priorities) <= VK_MAX_GLOBAL_PRIORITY_SIZE_KHR);
prop->priorityCount = ARRAY_SIZE(radv_global_queue_priorities);
memcpy(&prop->priorities, radv_global_queue_priorities, sizeof(radv_global_queue_priorities));
break;
@ -2761,20 +2761,20 @@ radv_GetMemoryHostPointerPropertiesEXT(
}
static enum radeon_ctx_priority
radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoKHR *pObj)
{
/* Default to MEDIUM when a specific global priority isn't requested */
if (!pObj)
return RADEON_CTX_PRIORITY_MEDIUM;
switch (pObj->globalPriority) {
case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_KHR:
return RADEON_CTX_PRIORITY_REALTIME;
case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
case VK_QUEUE_GLOBAL_PRIORITY_HIGH_KHR:
return RADEON_CTX_PRIORITY_HIGH;
case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_KHR:
return RADEON_CTX_PRIORITY_MEDIUM;
case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
case VK_QUEUE_GLOBAL_PRIORITY_LOW_KHR:
return RADEON_CTX_PRIORITY_LOW;
default:
unreachable("Illegal global priority value");
@ -2785,7 +2785,7 @@ radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *p
int
radv_queue_init(struct radv_device *device, struct radv_queue *queue, int idx,
const VkDeviceQueueCreateInfo *create_info,
const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
const VkDeviceQueueGlobalPriorityCreateInfoKHR *global_priority)
{
queue->device = device;
queue->priority = radv_get_queue_global_priority(global_priority);
@ -3394,8 +3394,8 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
/* Create one context per queue priority. */
for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
const VkDeviceQueueGlobalPriorityCreateInfoKHR *global_priority =
vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_KHR);
enum radeon_ctx_priority priority = radv_get_queue_global_priority(global_priority);
if (device->hw_ctx[priority])
@ -3409,8 +3409,8 @@ radv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo *pCr
for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
uint32_t qfi = queue_create->queueFamilyIndex;
const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
const VkDeviceQueueGlobalPriorityCreateInfoKHR *global_priority =
vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_KHR);
device->queues[qfi] =
vk_alloc(&device->vk.alloc, queue_create->queueCount * sizeof(struct radv_queue), 8,
@ -6500,7 +6500,7 @@ radv_tex_filter(VkFilter filter, unsigned max_ansio)
case VK_FILTER_LINEAR:
return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
: V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
case VK_FILTER_CUBIC_IMG:
case VK_FILTER_CUBIC_EXT:
default:
fprintf(stderr, "illegal texture filter");
return 0;
@ -6552,11 +6552,11 @@ static unsigned
radv_tex_filter_mode(VkSamplerReductionMode mode)
{
switch (mode) {
case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE:
return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
case VK_SAMPLER_REDUCTION_MODE_MIN:
return V_008F30_SQ_IMG_FILTER_MODE_MIN;
case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
case VK_SAMPLER_REDUCTION_MODE_MAX:
return V_008F30_SQ_IMG_FILTER_MODE_MAX;
default:
break;

2
src/amd/vulkan/radv_meta_blit2d.c
View File

@ -322,7 +322,7 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
};
const VkRenderingInfoKHR rendering_info = {
const VkRenderingInfo rendering_info = {
.sType = VK_STRUCTURE_TYPE_RENDERING_INFO,
.renderArea = {
.offset = { rects[r].dst_x, rects[r].dst_y },

2
src/amd/vulkan/radv_nir_lower_ray_queries.c
View File

@ -512,7 +512,7 @@ insert_traversal_triangle_case(struct radv_device *device, nir_builder *b, nir_s
nir_ssa_def *frontface = nir_flt(b, nir_imm_float(b, 0), div);
nir_ssa_def *switch_ccw =
nir_test_mask(b, rq_load_var(b, index, vars->candidate.sbt_offset_and_flags),
VK_GEOMETRY_INSTANCE_TRIANGLE_FRONT_COUNTERCLOCKWISE_BIT_KHR << 24);
VK_GEOMETRY_INSTANCE_TRIANGLE_FLIP_FACING_BIT_KHR << 24);
frontface = nir_ixor(b, frontface, switch_ccw);
rq_store_var(b, index, vars->candidate.frontface, frontface, 0x1);

2
src/amd/vulkan/radv_pipeline.c
View File

@ -4579,7 +4579,7 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
device->keep_shader_info;
struct radv_pipeline_stage stages[MESA_VULKAN_SHADER_STAGES] = {0};
VkPipelineCreationFeedbackEXT pipeline_feedback = {
VkPipelineCreationFeedback pipeline_feedback = {
.flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT,
};
bool noop_fs = false;

2
src/amd/vulkan/radv_pipeline_rt.c
View File

@ -1154,7 +1154,7 @@ insert_traversal_triangle_case(struct radv_device *device,
nir_ssa_def *frontface = nir_flt(b, nir_imm_float(b, 0), div);
nir_ssa_def *switch_ccw =
nir_test_mask(b, nir_load_var(b, trav_vars->sbt_offset_and_flags),
VK_GEOMETRY_INSTANCE_TRIANGLE_FRONT_COUNTERCLOCKWISE_BIT_KHR << 24);
VK_GEOMETRY_INSTANCE_TRIANGLE_FLIP_FACING_BIT_KHR << 24);
frontface = nir_ixor(b, frontface, switch_ccw);
nir_ssa_def *not_cull =

4
src/amd/vulkan/radv_private.h
View File

@ -2201,7 +2201,7 @@ struct radv_pipeline_stage {
struct radv_shader_info info;
struct radv_shader_args args;
VkPipelineCreationFeedbackEXT feedback;
VkPipelineCreationFeedback feedback;
};
static inline bool
@ -2841,7 +2841,7 @@ bool radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *
int radv_queue_init(struct radv_device *device, struct radv_queue *queue, int idx,
const VkDeviceQueueCreateInfo *create_info,
const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority);
const VkDeviceQueueGlobalPriorityCreateInfoKHR *global_priority);
void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint bind_point,
struct radv_descriptor_set *set, unsigned idx);

2
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View File

@ -1528,7 +1528,7 @@ radv_amdgpu_ctx_create(struct radeon_winsys *_ws, enum radeon_ctx_priority prior
r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
if (r && r == -EACCES) {
result = VK_ERROR_NOT_PERMITTED_EXT;
result = VK_ERROR_NOT_PERMITTED_KHR;
goto fail_create;
} else if (r) {
fprintf(stderr, "radv/amdgpu: radv_amdgpu_cs_ctx_create2 failed. (%i)\n", r);

1
src/vulkan/registry/update-aliases.py
View File

@ -18,6 +18,7 @@ EXCLUDE_PATHS = [
# These files come from other repos, there's no point checking and
# fixing them here as that would be overwritten in the next sync.
'src/amd/vulkan/radix_sort/',
]