gallium: add AMD-specific compute TGSI enums
for tgsi_to_nir
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@ -108,6 +108,7 @@ const char *tgsi_semantic_names[TGSI_SEMANTIC_COUNT] =
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"SUBGROUP_GT_MASK",
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"SUBGROUP_LE_MASK",
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"SUBGROUP_LT_MASK",
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"CS_USER_DATA_AMD",
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};
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const char *tgsi_texture_names[TGSI_TEXTURE_COUNT] =
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@ -160,6 +161,7 @@ const char *tgsi_property_names[TGSI_PROPERTY_COUNT] =
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"CS_FIXED_BLOCK_DEPTH",
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"MUL_ZERO_WINS",
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"VS_BLIT_SGPRS_AMD",
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"CS_USER_DATA_COMPONENTS_AMD",
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};
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const char *tgsi_return_type_names[TGSI_RETURN_TYPE_COUNT] =
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@ -145,7 +145,7 @@ static void si_create_compute_state_async(void *job, int thread_index)
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sel->info.uses_block_size &&
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sel->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0;
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program->num_cs_user_data_dwords =
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sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
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sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
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void *ir_binary = si_get_ir_binary(sel);
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@ -2215,7 +2215,7 @@ void si_load_system_value(struct si_shader_context *ctx,
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break;
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}
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case TGSI_SEMANTIC_CS_USER_DATA:
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case TGSI_SEMANTIC_CS_USER_DATA_AMD:
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value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
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break;
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@ -4978,7 +4978,7 @@ static void create_function(struct si_shader_context *ctx)
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ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
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unsigned cs_user_data_dwords =
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shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_DWORDS];
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shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
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if (cs_user_data_dwords) {
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ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
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LLVMVectorType(ctx->i32, cs_user_data_dwords));
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@ -261,18 +261,12 @@ enum {
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/* Values from set_tess_state. */
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TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI = TGSI_SEMANTIC_COUNT,
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TGSI_SEMANTIC_DEFAULT_TESSINNER_SI,
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/* Up to 4 dwords in user SGPRs for compute shaders. */
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TGSI_SEMANTIC_CS_USER_DATA,
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};
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enum {
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/* Use a property enum that CS wouldn't use. */
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TGSI_PROPERTY_CS_LOCAL_SIZE = TGSI_PROPERTY_FS_COORD_ORIGIN,
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/* The number of used user data dwords in the range [1, 4]. */
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TGSI_PROPERTY_CS_USER_DATA_DWORDS = TGSI_PROPERTY_FS_COORD_PIXEL_CENTER,
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/* These represent the number of SGPRs the shader uses. */
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SI_VS_BLIT_SGPRS_POS = 3,
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SI_VS_BLIT_SGPRS_POS_COLOR = 7,
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@ -152,8 +152,8 @@ void *si_create_dma_compute_shader(struct pipe_context *ctx,
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struct ureg_src value;
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if (!is_copy) {
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ureg_property(ureg, TGSI_PROPERTY_CS_USER_DATA_DWORDS, inst_dwords[0]);
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value = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_CS_USER_DATA, 0);
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ureg_property(ureg, TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD, inst_dwords[0]);
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value = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_CS_USER_DATA_AMD, 0);
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}
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struct ureg_src tid = ureg_DECL_system_value(ureg, TGSI_SEMANTIC_THREAD_ID, 0);
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@ -208,6 +208,7 @@ enum tgsi_semantic {
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TGSI_SEMANTIC_SUBGROUP_GT_MASK,
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TGSI_SEMANTIC_SUBGROUP_LE_MASK,
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TGSI_SEMANTIC_SUBGROUP_LT_MASK,
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TGSI_SEMANTIC_CS_USER_DATA_AMD,
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TGSI_SEMANTIC_COUNT, /**< number of semantic values */
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};
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@ -302,6 +303,7 @@ enum tgsi_property_name {
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TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
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TGSI_PROPERTY_MUL_ZERO_WINS,
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TGSI_PROPERTY_VS_BLIT_SGPRS_AMD,
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TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD,
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TGSI_PROPERTY_COUNT,
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};
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