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i965: Add nir channel_num system value 

v2:
 * simd16/32 fixes (curro)

Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Jordan Justen 2016-05-22 16:33:44 -07:00
parent 6f316c9d86
commit 8f48d23e0f
2 changed files with 16 additions and 0 deletions
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1
src/compiler/nir/nir_intrinsics.h
View File

@ -304,6 +304,7 @@ SYSTEM_VALUE(work_group_id, 3, 0, xx, xx, xx)
SYSTEM_VALUE(user_clip_plane, 4, 1, UCP_ID, xx, xx)
SYSTEM_VALUE(num_work_groups, 3, 0, xx, xx, xx)
SYSTEM_VALUE(helper_invocation, 1, 0, xx, xx, xx)
SYSTEM_VALUE(channel_num, 1, 0, xx, xx, xx)
/*
* Load operations pull data from some piece of GPU memory. All load

15
src/mesa/drivers/dri/i965/brw_fs_nir.cpp
View File

@ -3876,6 +3876,21 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
break;
}
case nir_intrinsic_load_channel_num: {
fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UW);
dest = retype(dest, BRW_REGISTER_TYPE_UD);
const fs_builder allbld8 = bld.group(8, 0).exec_all();
allbld8.MOV(tmp, brw_imm_v(0x76543210));
if (dispatch_width > 8)
allbld8.ADD(byte_offset(tmp, 16), tmp, brw_imm_uw(8u));
if (dispatch_width > 16) {
const fs_builder allbld16 = bld.group(16, 0).exec_all();
allbld16.ADD(byte_offset(tmp, 32), tmp, brw_imm_uw(16u));
}
bld.MOV(dest, tmp);
break;
}
default:
unreachable("unknown intrinsic");
}