KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

intel/compiler: add flag to indicate edge flags vertex input is last 

965 and the mesa st disagree on how vertex elements are ordered when
edgeflags are involved. 965 wants them in gl_vert_attrib order,
but gallium supplies the edgeflag as the last vertex element regardless.

This adds a flag which is enabled for gen4/5 to denote that the
edgeflag is at the end. When we reap 965 later we can resolve this
better.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11146>
This commit is contained in:
Dave Airlie 2021-06-08 15:04:42 +10:00 committed by Dave Airlie
parent 5f03570eaa
commit 8da92b5c0a
4 changed files with 14 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/intel/compiler/brw_compiler.h
View File

@ -1472,6 +1472,7 @@ struct brw_compile_vs_params {
const struct brw_vs_prog_key *key;
struct brw_vs_prog_data *prog_data;
bool edgeflag_is_last; /* true for gallium */
bool shader_time;
int shader_time_index;

13
src/intel/compiler/brw_nir.c
View File

@ -160,6 +160,7 @@ remap_patch_urb_offsets(nir_block *block, nir_builder *b,
void
brw_nir_lower_vs_inputs(nir_shader *nir,
bool edgeflag_is_last,
const uint8_t *vs_attrib_wa_flags)
{
/* Start with the location of the variable's base. */
@ -270,8 +271,16 @@ brw_nir_lower_vs_inputs(nir_shader *nir,
* before it and counting the bits.
*/
int attr = nir_intrinsic_base(intrin);
int slot = util_bitcount64(nir->info.inputs_read &
BITFIELD64_MASK(attr));
uint64_t inputs_read = nir->info.inputs_read;
int slot = -1;
if (edgeflag_is_last) {
inputs_read &= ~BITFIELD64_BIT(VERT_ATTRIB_EDGEFLAG);
if (attr == VERT_ATTRIB_EDGEFLAG)
slot = num_inputs - 1;
}
if (slot == -1)
slot = util_bitcount64(inputs_read &
BITFIELD64_MASK(attr));
nir_intrinsic_set_base(intrin, slot);
break;
}

1
src/intel/compiler/brw_nir.h
View File

@ -105,6 +105,7 @@ void brw_nir_lower_legacy_clipping(nir_shader *nir,
int nr_userclip_plane_consts,
struct brw_stage_prog_data *prog_data);
void brw_nir_lower_vs_inputs(nir_shader *nir,
bool edgeflag_is_last,
const uint8_t *vs_attrib_wa_flags);
void brw_nir_lower_vue_inputs(nir_shader *nir,
const struct brw_vue_map *vue_map);

2
src/intel/compiler/brw_vec4.cpp
View File

@ -2905,7 +2905,7 @@ brw_compile_vs(const struct brw_compiler *compiler,
prog_data->inputs_read = nir->info.inputs_read;
prog_data->double_inputs_read = nir->info.vs.double_inputs;
brw_nir_lower_vs_inputs(nir, key->gl_attrib_wa_flags);
brw_nir_lower_vs_inputs(nir, params->edgeflag_is_last, key->gl_attrib_wa_flags);
brw_nir_lower_vue_outputs(nir);
brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled,
key->base.robust_buffer_access);