ac: add radeon_info::tcc_harvested
Cc: 19.2 <mesa-stable@lists.freedesktop.org> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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@ -470,6 +470,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
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}
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}
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if (info->chip_class >= GFX10) {
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if (info->chip_class >= GFX10) {
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info->tcc_cache_line_size = 128;
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info->tcc_cache_line_size = 128;
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/* This is a hack, but it's all we can do without a kernel upgrade. */
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info->tcc_harvested =
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(info->vram_size / info->num_tcc_blocks) != 512*1024*1024;
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} else {
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} else {
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info->tcc_cache_line_size = 64;
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info->tcc_cache_line_size = 64;
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}
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}
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@ -694,6 +697,7 @@ void ac_print_gpu_info(struct radeon_info *info)
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printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
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printf(" num_sdma_rings = %i\n", info->num_sdma_rings);
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printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
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printf(" clock_crystal_freq = %i\n", info->clock_crystal_freq);
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printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
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printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
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printf(" tcc_harvested = %u\n", info->tcc_harvested);
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printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
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printf(" use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
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printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
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printf(" use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
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@ -58,6 +58,7 @@ struct radeon_info {
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uint32_t num_sdma_rings;
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uint32_t num_sdma_rings;
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uint32_t clock_crystal_freq;
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uint32_t clock_crystal_freq;
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uint32_t tcc_cache_line_size;
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uint32_t tcc_cache_line_size;
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bool tcc_harvested;
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bool has_clear_state;
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bool has_clear_state;
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bool has_distributed_tess;
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bool has_distributed_tess;
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bool has_dcc_constant_encode;
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bool has_dcc_constant_encode;
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